NetFPGA-based load balancer for a multi-stage router architecture

Atalla, Shadi; Bianco, A.; Birke, Robert; Giraudo, Luca

doi:10.1109/wccais.2014.6916593

Cited by 5 publications

(1 citation statement)

References 15 publications

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“…It is worth emphasizing that it is possible to support even higher line rates by switching to faster hardware. As far as the last point is concerned, Application-Specific Integrated Circuits (ASICs) are usually 4 times faster than FPGA (with a 30 times smaller area) [21,7,6]. The main contributions of this paper are: i) design, implementation and test of advanced low-level packet manipulation mechanisms, ii) integration of an hardware solution into an existing distributed router architecture obtaining performance improvements and iii) identification of a design issue in the NetFPGA board (e.g.…”

Section: Introductionmentioning

confidence: 99%

A Load Balancer for a Multi-Stage Router Architecture

Atalla¹,

Bianco²,

Birke³

et al. 2014

IJCA

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Multi-stage software router architectures permit to overcome several limitations inherent to single stage software routers. One of the key elements of the multi-stage architecture under study are the load balancers, which are used to distribute the load among backend routers. However, using a PC (Personal Computer) as a load balancer could create a performance bottleneck in the overall architecture. Since the operations performed by the load balancer are simple, we explore the possibility of an hardware-based implementation of load balancing functionality with the goal of improving its performance. In this paper, we describe the architecture of an FPGA-based load balancer and we present some performance results of its prototype implementation.

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Section: Introductionmentioning

confidence: 99%