Methods to Increase Fault Tolerance of Combinational Integrated Microcircuits by Redundancy Coding

Gavrilov, S. V.; Gurov, Sergey V.; Zhukova, T.D.; Rukhlov, V. S.; Ryzhova, D.I.; Telpukhov, Dmitry

doi:10.1007/s10598-017-9372-3

Cited by 5 publications

(2 citation statements)

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“…Developed algorithm begins with formation of a square symmetric matrix C of order k interdependence of errors at outputs [17]. Elements cij of matrix C are quantities (or quantities proportional to them) of error vectors, having simultaneously in i-th and j-th digits, 1≤i≤k, i + 1≤j≤k.…”

Section: Fig 2 Circuit Structure: Set Of Outputs Split Into Groups;mentioning

confidence: 99%

Automated Synthesis of Fault-Tolerant CED Circuits Based on R-code

Telpukhov

Zhukova

Demeneva

et al. 2019

MES

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Annotation-At present, issues related to synthesis of faulttolerant combinational circuits resistant to single failures acquire special urgency. This largely reflects various factors of microelectronic industry progress, together with the stateof-art in CAD tools development. Such factors as transition to nanometric design standards, greater clock frequency, lower supply voltage and also development of modern methods and means of automation, among other things, lead to the fact that combinational circuits are becoming the most vulnerable chip area. Often, redundant encoding methods, which are traditionally used in data storage and transmission systems, are used to solve the problem of fault tolerance of logic circuits. However, standard fault-tolerant codes are usually ineffective due to specific design and operation of combinational circuits. In this paper, a new approach to the construction of fault-tolerant combinational circuits using redundant coding based on the spectral R code is proposed. Application of technological protection methods for a part of the encoder allows this code, above all, to correct any single error in combinational circuit, and also to detect a double error in it. As the result, we build circuits with lower structural redundancy compared to circuits obtained through the traditional Triple Modular Redundancy (TMR) method. In addition, to reduce the probability of multiple errors, this article proposes a method based on outputs clustering of combinational circuit. In this paper, a number of experiments are described that demonstrate high effectiveness of the proposed approaches.

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Section: Fig 2 Circuit Structure: Set Of Outputs Split Into Groups;mentioning

confidence: 99%

Automated Synthesis of Fault-Tolerant CED Circuits Based on R-code

Telpukhov

Zhukova

Demeneva

et al. 2019

MES

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“…When constructing automation systems, methods for detecting and correcting errors in the computed values of the working functions of blocks and components are widely used [1][2][3][4]. The use of correction circuits requires the introduction of considerable redundancy determined by the need to compare the results of calculations from several circuits at once.…”

Section: Introductionmentioning

confidence: 99%

Boolean-Complement Based Fault-Tolerant Electronic Device Architectures

Ефанов

Sapozhnikov

2021

Autom Remote Control

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We propose new fault-tolerant architectures, which, in contrast to the well-known double and triple modular redundancy architectures, include only one copy of the original circuit. In the new architectures, a signal error detection circuit is used to select the functions to be corrected. The circuit is built on the basis of the Boolean complement method with parity check of calculations. A generalized architecture with Boolean complement based signal correction is presented. This architecture permits one to design the simplest fault-tolerant circuits. Algorithms for designing signal error detection circuits, as well as examples of their application, are given.

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