Automated Synthesis of Fault-Tolerant CED Circuits Based on R-code

Abstract

Annotation-At present, issues related to synthesis of faulttolerant combinational circuits resistant to single failures acquire special urgency. This largely reflects various factors of microelectronic industry progress, together with the stateof-art in CAD tools development. Such factors as transition to nanometric design standards, greater clock frequency, lower supply voltage and also development of modern methods and means of automation, among other things, lead to the fact that combinational circuits are becoming the most vulnerable chip area. Often, redundant encoding methods, which are traditionally used in data storage and transmission systems, are used to solve the problem of fault tolerance of logic circuits. However, standard fault-tolerant codes are usually ineffective due to specific design and operation of combinational circuits. In this paper, a new approach to the construction of fault-tolerant combinational circuits using redundant coding based on the spectral R code is proposed. Application of technological protection methods for a part of the encoder allows this code, above all, to correct any single error in combinational circuit, and also to detect a double error in it. As the result, we build circuits with lower structural redundancy compared to circuits obtained through the traditional Triple Modular Redundancy (TMR) method. In addition, to reduce the probability of multiple errors, this article proposes a method based on outputs clustering of combinational circuit. In this paper, a number of experiments are described that demonstrate high effectiveness of the proposed approaches.