Methodology for Realizing VMM with Binary RRAM Arrays: Experimental Demonstration of Binarized-ADALINE using OxRAM Crossbar

Kingra, Sandeep Kaur; Parmar, Vivek; Negi, Shubham; Khan, Sufyan; Hudec, Boris; Hou, Tuo‐Hung

doi:10.1109/iscas45731.2020.9180915

Cited by 5 publications

(3 citation statements)

References 25 publications

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“…By limiting the current during the set operation of the 1T1R cell with a lower gate voltage, the influence of LRS variation was reduced, and the propagation efficiency was increased, thereby further improving the HW-BNN. Kingra et al (2020) demonstrated hardware-based BNN with the fabricated 8 × 8 OxRAM passive array, wherein the resistance state distribution and VMM results. To achieve analog inputs by using PWM encoding, a BNN-based ADALINE classifier was used to mitigate non-idealities by comparing the experimental (67.54%) and simulation accuracy (78.07%) classification accuracy results for the UCI Cancer dataset.…”

Section: Compensation Methods Against Hardware Non-idealitiesmentioning

confidence: 99%

A comprehensive review of advanced trends: from artificial synapses to neuromorphic systems with consideration of non-ideal effects

Kim,

Song,

Hwang

et al. 2024

Front. Neurosci.

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A neuromorphic system is composed of hardware-based artificial neurons and synaptic devices, designed to improve the efficiency of neural computations inspired by energy-efficient and parallel operations of the biological nervous system. A synaptic device-based array can compute vector–matrix multiplication (VMM) with given input voltage signals, as a non-volatile memory device stores the weight information of the neural network in the form of conductance or capacitance. However, unlike software-based neural networks, the neuromorphic system unavoidably exhibits non-ideal characteristics that can have an adverse impact on overall system performance. In this study, the characteristics required for synaptic devices and their importance are discussed, depending on the targeted application. We categorize synaptic devices into two types: conductance-based and capacitance-based, and thoroughly explore the operations and characteristics of each device. The array structure according to the device structure and the VMM operation mechanism of each structure are analyzed, including recent advances in array-level implementation of synaptic devices. Furthermore, we reviewed studies to minimize the effect of hardware non-idealities, which degrades the performance of hardware neural networks. These studies introduce techniques in hardware and signal engineering, as well as software-hardware co-optimization, to address these non-idealities through compensation approaches.

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Section: Compensation Methods Against Hardware Non-idealitiesmentioning

confidence: 99%

A comprehensive review of advanced trends: from artificial synapses to neuromorphic systems with consideration of non-ideal effects

Kim,

Song,

Hwang

et al. 2024

Front. Neurosci.

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“…Binary/Ternary Neural Networks (BNN/TNN) [5]- [8] has created an opportunity to realize computational benefits by exploiting inherent analog computing capabilities of emerging resistive memories [9], [10]. Some of the NVM (non-volatile memory) technologies explored for IMC applications for analog multiplication include: Flash [11], [12], RRAM (resistive random access memory) [3], [13]- [16], and MRAM (magnetoresistive RAM) [17], [18]. RRAM based XNOR bitcells provide following advantages: (i) less area and non-volatility compared to SRAM (≈150 F 2 per bitcell), (ii) lower operating voltages and faster memory access time compared to Flash, and (iii) lower fabrication cost, reduced area and write energy compared to MRAM.…”

Section: Introductionmentioning

confidence: 99%

Time-Multiplexed In-Memory Computation Scheme for Mapping Quantized Neural Networks on Hybrid CMOS-OxRAM Building Blocks

Kingra

Parmar

Sharma

2022

IEEE Trans. Nanotechnology

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In this work, we experimentally demonstrate two key building blocks for realizing Binary/Ternary Neural Networks (BNNs/TNNs): (i) 130 nm CMOS based sigmoidal neurons and (ii) HfOx based multi-level (MLC) OxRAM-synaptic blocks. An optimized vector matrix multiplication programming scheme that utilizes the two building blocks is also presented. Compared to prior approaches that utilize differential synaptic structures, a single device per synapse with two sets of READ operations is used. Proposed hardware mapping strategy shows performance change of <5% (decrease of 2-5% for TNN, increase of 0.2% for BNN) compared to ideal quantized neural networks (QNN) with significant memory savings in the order of 16-32× for classification problem on Fashion MNIST (FMNIST) dataset. Impact of OxRAM device variability on the performance of Hardware QNN (BNN/TNN) is also analyzed.

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“…Among others, Mehonic et al [17] reported hand-written digit recognition with up to 97% accuracy ratio using an RRAM-based ANN. However, to our best knowledge, the overall assessment of the RRAM MAC operation in a simulation environment is not yet fully performed and includes several simplifications due to the limits of the underlying hardware model [18], [19], [20], [21], [22]. Recently, Bengel et al [23] experimentally analyzed the impact of binary RRAM nonidealities in VMM operations highlighting the fact that the low resistive state (LRS) variability plays a major role compared to the high resistive state (HRS) variability when performing MAC operations.…”

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confidence: 99%

Experimental Assessment of Multilevel RRAM-Based Vector-Matrix Multiplication Operations for In-Memory Computing

Quesada

Mahadevaiah

Rizzi

et al. 2023

IEEE Trans. Electron Devices

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Resistive random access memory (RRAM)based hardware accelerators are playing an important role in the implementation of in-memory computing (IMC) systems for artificial intelligence applications. The latter heavily rely on vector-matrix multiplication (VMM) operations that can be efficiently boosted by RRAM devices. However, the stochastic nature of the RRAM technology is still challenging real hardware implementations. To study the accuracy degradation of consecutive VMM operations, in this work we programed two RRAM subarrays composed of 8 × 8 one-transistor-one-resistor (1T1R) cells following two different distributions of conductive levels. We analyze their robustness against 1000 identical consecutive VMM operations and monitor the inherent devices' nonidealities along the test. We finally quantize the accuracy loss of the operations in the digital domain and consider the trade-offs between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities for future implementation of IMC hardware systems.

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Methodology for Realizing VMM with Binary RRAM Arrays: Experimental Demonstration of Binarized-ADALINE using OxRAM Crossbar

Cited by 5 publications

References 25 publications

A comprehensive review of advanced trends: from artificial synapses to neuromorphic systems with consideration of non-ideal effects

A comprehensive review of advanced trends: from artificial synapses to neuromorphic systems with consideration of non-ideal effects

Time-Multiplexed In-Memory Computation Scheme for Mapping Quantized Neural Networks on Hybrid CMOS-OxRAM Building Blocks

Experimental Assessment of Multilevel RRAM-Based Vector-Matrix Multiplication Operations for In-Memory Computing

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