Methodology for improvement of data retention in floating gate flash memory using leakage current estimation

Moon, Pyung; Lim, Jun Yeong; Youn, Tae Un; Noh, Keum Whan; Park, Sung Kye; Yun, Ilgu

doi:10.1016/j.microrel.2013.07.007

Cited by 5 publications

(2 citation statements)

References 8 publications

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“…The test structures are fabricated on 12-inch wafer using the 2x-nm NAND flash process by SK Hynix Semiconductor Inc. The tunneling oxide is grown on Si-substrate and the test structure of IPD is constructed with ONO stack sandwiched with two heavily doped poly-Si layers, which are the floating gate and the control gate (7). The silicon oxide (bottom), silicon nitride and silicon oxide (top) of ONO stack is sequentially grown by LPCVD.…”

Section: Methodsmentioning

confidence: 99%

Analysis of Intrinsic Retention Characteristics for 2x-Nm NAND Flash Memory Using TCAD Simulation

et al. 2014

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The retention characteristic of memory devices is an important issue as the size of the chip is scaled down continuously. However, it is hard to retain the reliable retention characteristic at smaller size of chip since the interference and leakage problems are induced by scaling down the chip. This paper suggests the main leakage mechanisms of 2x-nm flash memory at the pre-cycling situation by comparing the measurement Vth data with TCAD simulation to analyze this problem. Based on the results, we identify the failure mechanisms and factors which affect degradation of intrinsic retention characteristics.

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Section: Methodsmentioning

confidence: 99%