Methodology for fault grading high speed I/O interfaces used in complex Graphics Processing Unit

Abstract

Graphics Processing Unit (GPU) requires I/O bandwidth of the order of Gbps which can be met by implementation of High Speed Serializer/Deserializer differential I/Os with clock embedded in data stream, traditionally tested using functional Built In Self Test (BIST). Implementation of these I/Os on complex graphics chip poses requirement for fault grading these I/Os. This paper presents the challenges involved in fault grading SerDes I/Os used in Nvidia's GPU chips and proposes methodology for extracting fault coverage numbers using industry standard tools.