Methodological Framework for NoC Resources Dimensioning on FPGAs

Fresse, Virginie; Combes, Catherine; Payet, Matthieu; Rousseau, Frédéric

doi:10.1016/j.procs.2015.07.225

Cited by 5 publications

(4 citation statements)

References 14 publications

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“…The things are randomly assigned diverse hardware capabilities, in terms of computing, memory, energy storage, power and communication. Consequently the link rate of things ranges among [250, 10 , 10 4 ] kbps and the power of things varies among [10,30,50,80,100] milliwatts.…”

Section: Routing Phasementioning

confidence: 99%

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A Delta diagram synthesis for IoT optimization with grey wolf driven multi-objective automation

Siddavaatam¹

2021

Preprint

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Today, Internet of Things (IoT) is a major paradigm shift that will mark an epoch in communication technology such that every physical object can be connected to the Internet. With the advent of 5G communications, IoT is in urgent need of optimized architectures that can efficiently support wide ranging heterogeneous multi-objective requirements of communication, hardware and security aspects. The optimization challenges are rooted in the technology and how the information is acquired and manipulated by this technology. My research in this thesis provides a description of compelling challenges faced by IoT and how to mitigate these challenges by designing resource-aware communication protocols, resource- constrained device hardware with low computing power and low-powered computational security enhancements. This thesis lays the foundation for optimizing these challenging IoT paradigms by introducing a novel Delta-Diagram based synthesizing model. The Delta- Diagram provides a road-map linking the behavioral and structural domains of a given IoT paradigm to generate respective optimizer domain parameters, which can be utilized by any optimizer framework. The fundamental part of the communication synthesizer is a mathematical model, developed to obtain the best possible routing paths and communication parameters among things. The ultimate aim of the entire synthesis process is to devise a design automation tool for IoT, which exploits the interrelations between different layer functionalities. This thesis also proposes a novel cross-layer Grey wolf optimizer for IoT, which outperforms some of the contemporary optimizer algorithms such as Particle Swarm, Genetic Algorithm, Differential Evolution optimizers in solving unimodal, multi-modal and composition benchmark problems. The purpose of this optimizer is to accurately capture both the high heterogeneity of the IoT and the impact of the Internet as part of delta diagram synthesis enabled network architecture. In addition, the Grey wolf optimizer for IoT plays a crucial role in design exploration of system on chip architecture for IoT device hardware. The results generated by the optimizer yielded the most optimum feasible solutions in the design space exploration process of the IoT.

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Section: Routing Phasementioning

confidence: 99%

“…The main challenge in DSE arises from the sheer size of the design space that must be explored. Typically, a large system has millions, if not billions, of possibilities, and so enumerating every point in the design space is prohibitive [79,80].…”

Section: Introductionmentioning

confidence: 99%

A Delta diagram synthesis for IoT optimization with grey wolf driven multi-objective automation

Siddavaatam¹

2021

Preprint

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“…The NoC infrastructure has a 2D mesh topology and has been designed to be regular in terms of resources consumption [11] for estimation purposes. Our NoC uses a wormhole packet switching technique to carry packets.…”

Section: Noc Infrastructurementioning

confidence: 99%

Dynamic data flow analysis for NoC based application synthesis

Payet¹,

Fresse²,

Rousseau

et al. 2015

2015 International Symposium on Rapid System Prototyping (RSP)

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Network-on-Chip (NoC) is an interesting communication fabric for multi processing element architectures that benefits from the parallelism of algorithms. We present a method that uses a symbolic execution technique to extract the parallelism of an application to be mapped on FPGAs using the flexibility of a NoC communication infrastructure and the properties of a high level programming language. An application specific hardware is then generated using a High Level Synthesis flow. We provide a dedicated mechanism for data paths reconfiguration that allows different applications to run on the same set of processing elements. Thus, the output design is programmable and has a processor-less distributed control. This approach of using NoCs enables us to automatically design generic architectures that can be used on FPGA servers for High Performance Reconfigurable Computing. We validate our method on binomial tree applications used for option pricing on FPGAs.

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“…The first paper is on "NoC Dimensioning from mathematical models" with authors Virginie Fresse, Catherine Combes, Matthieu Payet and Frédéric Rousseau. They propose a mathematical framework that models the relationship between an application task graph, the communication architecture and the resource usage on platform (FPGA in this case) [7]. The next paper, "The Performance of NoCs for Very Large Manycore Systems under Locality-based Traffic," by Sharifa Al Khanjari and Wim Vanderbauwhede studies latency and throughput of NoCs based on well-known topologies under assumptions of physical data expected in 2023 and http://dx.doi.org/10.12785/ijcds/050201 http://journals.uob.edu.bh and governmental agencies.…”

Section: Introductionmentioning

confidence: 99%

Introduction to Special Issue: Design and Performance of Networks on Chip

Abdallah

Vaidyanathan

Ariwa³

et al. 2016

IJCDS

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http://journals.uob.edu.bh underscores the importance of communication locality [8]. The third paper is entitled "Group based Shortest Path Routing Algorithm for Hierarchical Cross Connected Recursive Networks (HCCR)" and is authored by Omair Inam, Sharifa Al Khanjari, Wim Vanderbauwhede and proposes the Hierarchical Cross Connected Recursive network. The paper develops topological properties of the network and studies its performance for Group-Based shortest path routing [9]. The fourth paper by Michael O. Agyeman, Kenneth Tong and Terrence Mak is entitled "An Improved Wireless Communication Fabric for Performance Aware Network-on-Chip Architectures." It studies device-level changes to improve the performance of wireless NoCs [10]. The final paper by Jawwad Latif, Sadia Azam, Hassan N. Chaudhry and Tahir Muhammad is entitled "Performance Evaluation of Modern Network-on-Chip Router Architectures." This paper explores the application of switch folding to Dual Xbar routers, showing tradeoffs between buffer energy and performance [11]. The final paper, "Embedded Systems Design Using Event-B Theories," is authored by Abdelhamid Hariche, Mostafa Belarbi and Abdallah Chouarfia. It studies a framework for modeling aspects of embedded systems, including NoCs, managing design complexity through abstraction and refinement.

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Methodological Framework for NoC Resources Dimensioning on FPGAs

Cited by 5 publications

References 14 publications

A Delta diagram synthesis for IoT optimization with grey wolf driven multi-objective automation

A Delta diagram synthesis for IoT optimization with grey wolf driven multi-objective automation

Dynamic data flow analysis for NoC based application synthesis

Introduction to Special Issue: Design and Performance of Networks on Chip

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