Method for Formal Verification of Soft-Error Tolerance Mechanisms in Pipelined Microprocessors

Formal verification of safety of polymorphic heterogeneous multi-core architectures

“…Abstractions of cores that can have more than two BB in execution can be constructed similarly. Note that Correspondence Checking has already been applied efficiently to formally verify individual cores of many architectures: single issue pipelined [21 -24, 28], in-order superscalar [23,24,26,28], out-of-order superscalar [27,30], and VLIW [25,28], including designs with soft-error tolerance mechanisms [42], reconfigurable functional units [43], arrays of reconfigurable functional units [44], and multithreaded execution [45].…”

“…A VLIW processor imitating the Intel Itanium [12,20] in many features, and that could have more than 200 RISC-like instructions in execution, was formally verified in [25,39]. Techniques for automatic formal verification of pipelined processors with hardware mechanisms for soft-error tolerance [4,9] were presented in [42], and with multithreaded execution in [45].…”