Exploiting Abstraction for Efficient Formal Verification of DSPs with Arrays of Reconfigurable Functional Units

Formal verification of safety of polymorphic heterogeneous multi-core architectures

“…Abstractions of cores that can have more than two BB in execution can be constructed similarly. Note that Correspondence Checking has already been applied efficiently to formally verify individual cores of many architectures: single issue pipelined [21 -24, 28], in-order superscalar [23,24,26,28], out-of-order superscalar [27,30], and VLIW [25,28], including designs with soft-error tolerance mechanisms [42], reconfigurable functional units [43], arrays of reconfigurable functional units [44], and multithreaded execution [45].…”