Random test program generation for verification and validation of the Samsung Reconfigurable Processor

Egger, Bernhard; Song, Eunjin; Lee, Hochan; Shin, Dae-Yong

doi:10.1016/j.sysarc.2019.05.007

Cited by 2 publications

(1 citation statement)

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“…Simulation‐based verification relies on the development of manually coded directed tests , and directed random simulation , that chooses random legal inputs for the design at a very high rate, based on a set of constraints mentioned in high‐level test templates. For example, the work reported in [15] describes a framework to verify the functional correctness of the Samsung Reconfigurable Processor. The test generator constructs an architectural model directly from the high‐level hardware description of the processor and the random test programs are generated by an edge‐centric place‐and‐route scheduler that operates on a graph representation of the architecture.…”

Section: Related Workmentioning

confidence: 99%

Automated planning for finding alternative bug traces

Jana

Dey

Mondal

et al. 2020

IET Computers & Digital Techniques

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Section: Related Workmentioning

confidence: 99%

Automated planning for finding alternative bug traces

Jana

Dey

Mondal

et al. 2020

IET Computers & Digital Techniques

View full text Add to dashboard Cite

Directed Test Generation for Hardware Validation: A Survey

Jayasena,

Mishra

2024

ACM Comput. Surv.

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The complexity of hardware designs has increased over the years due to the rapid advancement of technology coupled with the need to support diverse and complex features. The increasing design complexity directly translates to difficulty in verifying functional behaviors as well as non-functional requirements. Simulation is the most widely used form of validation using both random and constrained-random test patterns. The random nature of test sequences can cover a vast majority of scenarios, however, it can introduce unacceptable overhead to cover all possible functional and non-functional scenarios. Directed tests are promising to cover the remaining corner cases and hard-to-detect scenarios. Manual development of directed tests can be time consuming and error-prone. A promising avenue is to perform automated generation of directed tests. In this paper, we provide a comprehensive survey of directed test generation techniques for hardware validation. Specifically, we first introduce the complexity of hardware verification to highlight the need for directed test generation. Next, we describe directed test generation using various automated techniques, including formal methods, concolic testing, and machine learning. Finally, we discuss how to effectively utilize the generated test patterns in different validation scenarios, including pre-silicon functional validation, post-silicon debug, as well as validation of non-functional requirements.

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Random test program generation for verification and validation of the Samsung Reconfigurable Processor

Cited by 2 publications

References 40 publications

Automated planning for finding alternative bug traces

Automated planning for finding alternative bug traces

Directed Test Generation for Hardware Validation: A Survey

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