Metal-organic chemical vapor deposition growth of InGaN/GaN high power green light emitting diode: Effects of InGaN well protection and electron reservoir layer

Abstract

We investigated the effects of the well protection layer (WPL) and electron reservoir layer (ERL) on the emission properties of InGaN/GaN green multiple quantum wells (MQWs). In order to increase their emission wavelength by preventing the volatile InGaN well, a thin GaN WPL was coated subsequently on each well layer at the same temperature before ramping-up the temperature to grow the GaN barrier. It was found that the WPL directly influenced the indium content and optical properties of the MQW. The indium content was in fact increased, as was evident from the x-ray diffraction and photoluminescence experiments. Then, to explore the possibility of enhancing the quantum efficiency by increasing the electron capture rate, a superlattice ERL composed of ten pairs of InGaN/GaN was embedded between the MQW and n-GaN. The electroluminescence intensity of the green light emitting diode with the ERL was up to three times higher than that of the diode without the ERL. These results imply that the carrier capture by the MQW is significantly improved by the additional superlattice ERL, which consequently leads to the enhancement of the quantum efficiency.

The effect of nanometre-scale V-pits on electronic and optical properties and efficiency droop of GaN-based green light-emitting diodes

“…and Ju et al . reported that an InGaN or InGaN/GaN underlayer can behave as an electron reservoir, leading to an enhancement of the electron capture efficiency 26 , 27 . Akasaka et al .…”

Generated Carrier Dynamics in V-Pit-Enhanced InGaN/GaN Light-Emitting Diode

“…Additionally, incorporation of InGaN/GaN strain-relief layers, such as strainedlayer superlattices (SLSs) or low InN content layers, have been explored as a means to increase InGaN LED efficiency by suppressing built-in polarization fields in the MQW region. [20][21][22] SLS layers have previously been used to regulate the growth of thin quantum wells in V-pits with characteristic ሼ101 ത 1ሽ facets. [23][24][25] However, the effects of V-pits on the carrier dynamics and droop mechanism in III-nitride LEDs are presently not fully understood.…”

“…One of the most prominent efforts focused on a patterned sapphire substrate (PSS) that results in stress relaxation of the GaN epilayers and the reduction of threading dislocation (TD) density, leading to efficiency improvement. − Other approaches, based on inclusion of p-AlGaN , or p-InGaN/AlGaN electron blocking layers (EBL) above the multi-quantum-well (MQW) LED structure, were found to enhance efficiency. Additionally, incorporation of InGaN/GaN strain-relief layers, such as strained-layer superlattices (SLSs) or low InN content layers, has been explored to increase InGaN LED efficiency by suppressing built-in polarization fields in the MQW region. − SLS layers have previously been used to regulate the growth of thin quantum wells in V-pits with characteristic {10-11} facets. − However, the effects of V-pits on the carrier dynamics and droop mechanism in III-nitride LEDs are presently not fully understood.…”

Interface modification of the InGaN/GaN quantum wells: the strain pre-relief effect

“…Great efforts have been made to improve the material quality, and to enhance the indium incorporation efficiency and quantum efficiency of green LEDs by the reduction of pit density, increase of surface/interface qualities and suppressing phase separation/aggregation of high indium content InGaN materials [11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27]. As the indium-rich inclusions and the related pits would cause loss of interface abruptness and reduce the device quality, several techniques have been developed towards suppression of embedded inclusions, e.g.…”

“…Accordingly, improvement of the InGaN-to-GaN interface quality would be desirable for the subsequent growth of InGaN/GaN MQWs and the device quality. Recently interface modification by insertion of a low-temperature (LT) GaN layer (about 3-5 nm) between the InGaN well and the GaN barrier has been employed for suppressing the indium loss during the temperature ramping and high-temperature (HT) growth of GaN barriers [24][25][26][27].…”