Metal gate-HfO/sub 2/ MOS structures on GaAs substrate with and without Si interlayer

Determining weak Fermi-level pinning in MOS devices by conductance and capacitance analysis and application to GaAs MOS devices

“…MOSFETs based on GaAs are currently investigated as a promising route to enhance CMOS because of their superior charge transport characteristics [1][2][3][4][5][6][7][8][9]. The successful development of deposited oxides for Si CMOS has stimulated GaAs MOSFET research [5][6][7][8][9].…”

“…The successful development of deposited oxides for Si CMOS has stimulated GaAs MOSFET research [5][6][7][8][9]. A major obstacle in obtaining a superior GaAs MOSFET is the occurrence of Fermi-level pinning [9][10][11][12], which prevents proper MOS-FET operation.…”

Performance enhancement of n-channel inversion type InxGa1−xAs metal-oxide-semiconductor field effect transistor using ex situ deposited thin amorphous silicon layer

“…These include molecular beam epitaxy ͑MBE͒ deposition of Ga 2 O 3 ͑Refs. 1-4͒, in situ [5][6][7] and ex situ 8,9 deposition of amorphous Si ͑a-Si͒ or Ge interlayers, 10,11 atomic hydrogen cleaning of the surface, 12,13 and deposition of different dielectrics in direct contact with the substrate. 14-18 However, the fabrication of III-V based devices is still challenging and significant effort is required to get the best performance.…”

Optimization of electrical characteristics of TiO2-incorporated HfO2 n-type doped gallium arsenide metal oxide semiconductor capacitor with silicon interface passivation layer

“…Recently, III-V-based MOSFETs using high-k dielectrics such as HfO 2 have been investigated. 3 However, very little work has been done on multimetal bilayer dielectrics for III-V MOSFET applications. In this letter, we present the electrical characteristics of TiO 2 / HfO 2 bilayer MOS Capacitor ͑MOSCap͒ on GaAs substrate for reduced hysteresis and EOT.…”

“…It has been found that Si IPL is very effective in passivating GaAs surface resulted in low frequency dispersion and low D it . 3 Hf and Ti were then deposited using the modulation technique. 4 This was followed by postdeposition anneal at 600°C for 7 min, and a TaN gate electrode was then deposited using dc sputtering and patterned using photolithography and reactive ion etching.…”