MESIP: A Configurable and Data Reusable Motion Estimation Specific Instruction-Set Processor

Abstract

This paper proposes a new motion estimation (ME)-specific instruction-set processor (MESIP) with a novel search scan order with high data reusability, to efficiently implement various advanced ME algorithms. The proposed ME-specific instructions can be selectively used for ME algorithms. The novel data-reusing search scan order, called center biased search scan (CBSS), exploits the symmetry of the search pattern to reduce redundant data loading on MESIP by about 26.9% and 16.1% compared with raster scan and snake scan, respectively. MESIP has been implemented with IBM's 90-nm CMOS technology and has 203K gates excluding memory. Simulation results show that the proposed MESIP can reduce the number of required instructions by up to 18.9% compared with existing ME processors. Moreover, MESIP achieves comparable performance even with ME ASICs and hence may be quite suitable for a low-power and high-performance ME implementation.Index Terms-Application-specific instruction-set processor (ASIP), configurable architecture, low-power design, motion estimation/motion compensation (ME/MC), search scan order.

High-Performance Motion Estimation for Image Sensors with Video Compression

“…All the three levels have better data reuse efficiency than their intra-frame counterparts. Furthermore, the new method is compatible with different intra-frame data reuse schemes [20,21] and scan orders [22,23]. Comparing the inter-frame data reuse scheme with the intra-frame data reuse scheme, we find that the memory traffic can be reduced by 50% for VC-ME according to the case study.…”

“…Reusing data on chip is usually considered to reduce off-chip memory traffic. Some data reuse methods are proposed for FSIME [20,21,22,23,24]. Previous work mainly focused on intra-frame data reuse within a reference frame but inter-frame data reuse was neglected.…”

“…Previous work mainly focused on intra-frame data reuse within a reference frame but inter-frame data reuse was neglected. For VC-ME, the reconstructed frame was usually stored to off-chip memory and then loaded to on-chip memory when needed [23,25,26,27,28]. If the reconstructed frame is reused on chip without being stored to off-chip memory for VC-ME, the off-chip memory traffic will be greatly reduced.…”

Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures

“…2. Kim and Sunwoo [14] and Ansaloni et al [15] reduce the system clock frequency to ensure that both kinds of operations can be completed in one cycle. Thus, from PEs' point of view, the data loading latency is completely hidden by logic operations, as shown in Fig.…”

“…Then, for II ∈ [MII, ηII s ], we can estimate the lower bound of NLET (NLET − ) (line 18). After all η and II related to the matrix are traversed, the individuals in the next generation are generated by GA algorithm and the previous steps (lines [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22] are repeated. After the generation number exceeds the G max , we get the series of NLET − for all parameter sets ( , η, II).…”