MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks

Rajaram,; Jian, Pan

doi:10.1109/aspdac.2008.4483951

Cited by 35 publications

(70 citation statements)

References 11 publications

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“…Other approaches start with a fully uniform mesh, identify and remove redundant segments whose effect on variations is minimal by applying network theory techniques, thereby trading off variations with wire length. A set-cover problem is solved to obtain mesh pre-driver minimum buffers [10], [11]. The initial uniform grid is designed to ensure that metal redundancies within the grid satisfy target skew requirements [10].…”

Section: Related Workmentioning

confidence: 99%

“…A set-cover problem is solved to obtain mesh pre-driver minimum buffers [10], [11]. The initial uniform grid is designed to ensure that metal redundancies within the grid satisfy target skew requirements [10].…”

Section: Related Workmentioning

confidence: 99%

“…Non-uniform meshes [5], [10], [11] have been developed to save wire resources and power. Design automation and optimization of metal and power versus tolerance tradeoffs are discussed in [10], [11]. Mesh architectures differ in the locality of the mesh.…”

Section: Clock Meshesmentioning

confidence: 99%

“…Several proposals for optimizing non-tree distribution networks have been presented, employing either customized meshes [1][2][3][4][5][6][7] or automating the process of adding crosslinks to the clock tree to enhance tolerance and lower power [8], [9]. Yet other papers propose removing some edges from a mesh to reduce power while minimally increasing the skew [10], [11].…”

Section: Introductionmentioning

confidence: 99%

“…Non-tree clock distribution topologies (e.g., clock meshes) exhibit useful characteristics due to multi-path signal propagation created by routing redundancies [1][2][3][4][5][6][7][8][9][10][11]. These non-tree clock distribution networks are exploited to distribute the global clock signal over an integrated circuit, and exhibit high immunity to process, voltage, and temperature (PVT) variations, while tolerating non-uniform switching and an unbalanced distribution of the clocked elements.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Timing-driven variation-aware nonuniform clock mesh synthesis

Abdelhadi

Ginosar

Kolodny

et al. 2010

Proceedings of the 20th Symposium on Great Lakes Symposium on VLSI

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Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as meshes and crosslinks, are employed to reduce skew and also to mitigate skew variations. However, these networks incur an increase in dissipated power while consuming significant metal resources. Several methods have been proposed to trade off power and wires to reduce skew. In this paper, an efficient algorithm is presented to reduce skew variations rather than skew, and prioritize the algorithm for critical timing paths, since these paths are more sensitive to skew variations. The algorithm has been implemented for a standard 65 nm cell library using standard EDA tools, and has been tested on several benchmark circuits. As compared to other methods, experimental results show a 37% average reduction in metal consumption and 39% average reduction in power dissipation, while insignificantly increasing the maximum skew.

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Section: Related Workmentioning

confidence: 99%