MERO: A Statistical Approach for Hardware Trojan Detection

Abstract

Abstract. In order to ensure trusted in-field operation of integrated circuits, it is important to develop efficient low-cost techniques to detect malicious tampering (also referred to as Hardware Trojan) that causes undesired change in functional behavior. Conventional postmanufacturing testing, test generation algorithms and test coverage metrics cannot be readily extended to hardware Trojan detection. In this paper, we propose a test pattern generation technique based on multiple excitation of rare logic conditions at internal nodes. Such a statistical approach maximizes the probability of inserted Trojans getting triggered and detected by logic testing, while drastically reducing the number of vectors compared to a weighted random pattern based test generation. Moreover, the proposed test generation approach can be effective towards increasing the sensitivity of Trojan detection in existing side-channel approaches that monitor the impact of a Trojan circuit on power or current signature. Simulation results for a set of ISCAS benchmarks show that the proposed test generation approach can achieve comparable or better Trojan detection coverage with about 85% reduction in test length on average over random patterns.

A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans

“…In [9], Chakraborty et al propose to generate a set of test patterns that maximizes the chance to detect a HT. The proposed methodology is Called MERO (for Multiple Excitation of Rare Occurrence).…”

“…HTs detection methods are divided into two categories: methods based on side-channel analysis [7,8], or logic testing [6,9]. In the latter case, logic testing is performed before deployment in the field to try to detect the presence of potential HTs: if an erroneous behavior of the IC is observed, it can be inferred that a HT has been inserted in the IC.…”

Benchmarking of Hardware Trojans and Maliciously Affected Circuits

“…- [9][10][11][12]. However, the large number of states/inputs in modern designs limit the accuracy of these approaches, especially for Trojans that have extremely low trigger probability.…”

Hardware Attack Mitigation Techniques Analysis

“…However, this approach is time consuming and requires significant resources, so it is not practical to examine a large number of chips. In practice, defenders rely on non-destructive techniques to determine if a chip is working probably [7][8][9]. These techniques can be employed during testing and/or chip operation.…”