Memristor-Based (ReRAM) Data Memory Architecture in ASIP Design

Hartmann, Matthias; Raghavan, Praveen; Perre, Liesbet Van der; Agrawal, Prashant; Dehaene, Wim

doi:10.1109/dsd.2013.138

Cited by 8 publications

(6 citation statements)

References 10 publications

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“…Memristors [9] are passive two-port elements with variable resistance. Formally, a currentcontrolled time-invariant memristive system [7] is represented by…”

Section: Resistive Ram (Rram)mentioning

confidence: 99%

Accurate age counter for wear leveling on non-volatile based main memory

Luo

Zhuge

Shi

et al. 2013

Des Autom Embed Syst

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Limited lifetime has been a key challenge in development of emerging non-volatile memories (NVM). Age counter based wear leveling is the most effective approach in the extension of their lifetime. The age counters in these approaches are determined by the number of writes to an NVM management unit, such as segment, page or block, to represent the wearing to the NVM unit. However, age counters in previous works have a key problem, which is not able to accurately represent the real wearing. In addition, traditional wear leveling approaches are also unaware of intra-unit non-uniform writes. For these reasons, the existing wear-leveling methods are limited for extending the lifetime of NVM. To address these problems, this paper proposes an accurate age counter increment mechanism, which is designed with the awareness of flags overlap between the write buffer and physical NVM unit. Flags overlap means that the dirty flags of the updated data are overlapping with the wearing flags of the physical page. In this case, the age counter is increased. For intra-unit non-uniform writes, it is released by the smartly designed write buffer. Cooperating with the proposed age counter, this paper further develops an accurate age counter-aware wearleveling for non-volatile based main memory. Detailed simulations of 20 workloads show that the proposed mechanism is very encouraging. The accuracy of the proposed age counter is improved by 438.0 %, on average, compared to traditional age counters. In addition, we achieve 95.0 % of the lifetime to the theoretical maximum on average, while just incurring 8.1 % overhead compared to no wear leveling (baseline).

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“…Memristors [9] are passive two-port elements with variable resistance. Formally, a currentcontrolled time-invariant memristive system [7] is represented by…”

Section: Resistive Ram (Rram)mentioning

confidence: 99%

Accurate age counter for wear leveling on non-volatile based main memory

Luo

Zhuge

Shi

et al. 2013

Des Autom Embed Syst

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“…With the unveiling of on-chip memories such as memristors [1] and embedded DRAMs [2] the size of on-chip memory is getting a dramatic increase. As the amount of on-chip gates increases, there is a dramatic increase in size and architecture of local memories such as caches and scratchpads.…”

Section: Introductionmentioning

confidence: 99%

PAMS: Pattern Aware Memory System for embedded systems

Hussain

Sönmez

Palomar

et al. 2014

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)

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In this paper, we propose a hardware mechanism for embedded multi-core memory system called Pattern Aware Memory System (PAMS). The PAMS supports static and dynamic data structures using descriptors and specialized memory and reduces area, cost, energy consumption and hit latency. When compared with a Baseline Memory System, the PAMS consumes between 3 and 9 times and 1.13 and 2.66 times less program memory for static and dynamic data structures respectively. The benchmarking applications (having static and dynamic data structures) results show that PAMS consumes 20% less hardware resources, 32% less on chip power and achieves a maximum speedup of 52x and 2.9x for static and dynamic data structures respectively. The results show that the PAMS multi-core system transfers data structures up to 4.65x faster than the MicroBlaze baseline system.

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“…1(a)), there has been increasing interests in different aspects of memristor applications. To this end, memristors have been applied in areas such as high density memory design [3], [4], neuromorphic systems [5], [6], secure and crypto (e.g. Physical Unclonable Functions (PUF) etc.)…”

Section: Introductionmentioning

confidence: 99%

Novel techniques for memristive multifunction logic design

et al. 2019

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We present novel techniques for realising reliable low overhead logic functions and more complex systems based on the switching characteristics of memristors. Firstly, we show that memristive circuits have inherent properties for realising multiple valued MIN-MAX operations over the post algebra. We then present an efficient hybrid 1T-4M logic architecture for dual XOR/AND and XNOR/OR functionality, which can be seamlessly integrated with the existing CMOS technology. Although memristors are usually considered to operate at lower frequencies, however, recent advances in technology show their potentiality at high frequencies. To this end, we also explore the effects of high frequencies on their performance and thereby propose reliable high frequency design techniques based on our 1T-4M architectures. Experimental results, based on the design of full adders and multipliers over GF, show that the proposed designs require significantly lower power and overhead while maintaining reliable performance at low as well as at high frequencies compared to the existing techniques.

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Memristor-Based (ReRAM) Data Memory Architecture in ASIP Design

Cited by 8 publications

References 10 publications

Accurate age counter for wear leveling on non-volatile based main memory

Accurate age counter for wear leveling on non-volatile based main memory

PAMS: Pattern Aware Memory System for embedded systems

Novel techniques for memristive multifunction logic design

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