Accurate age counter for wear leveling on non-volatile based main memory

Abstract

Limited lifetime has been a key challenge in development of emerging non-volatile memories (NVM). Age counter based wear leveling is the most effective approach in the extension of their lifetime. The age counters in these approaches are determined by the number of writes to an NVM management unit, such as segment, page or block, to represent the wearing to the NVM unit. However, age counters in previous works have a key problem, which is not able to accurately represent the real wearing. In addition, traditional wear leveling approaches are also unaware of intra-unit non-uniform writes. For these reasons, the existing wear-leveling methods are limited for extending the lifetime of NVM. To address these problems, this paper proposes an accurate age counter increment mechanism, which is designed with the awareness of flags overlap between the write buffer and physical NVM unit. Flags overlap means that the dirty flags of the updated data are overlapping with the wearing flags of the physical page. In this case, the age counter is increased. For intra-unit non-uniform writes, it is released by the smartly designed write buffer. Cooperating with the proposed age counter, this paper further develops an accurate age counter-aware wearleveling for non-volatile based main memory. Detailed simulations of 20 workloads show that the proposed mechanism is very encouraging. The accuracy of the proposed age counter is improved by 438.0 %, on average, compared to traditional age counters. In addition, we achieve 95.0 % of the lifetime to the theoretical maximum on average, while just incurring 8.1 % overhead compared to no wear leveling (baseline).

Energy efficient IPC based dual compression for endurance enhancement of NVRAM as main memory in embedded devices

“…Many works are proposed to improve the endurance of NVRAM. Most of the proposed endurance improvement methods involve constantly monitoring the wear levels of all lines of memory or employing a coarse-grained wear-leveling based on a global counter, resulting in a device's enhancement being limited by the weakest endurance cell or erroneous wear-leveling [4][5][6][7][8][9][10][11]. The mentioned criticalities are addressed in the proposed framework in this paper.…”