Memory Technologies for Sub-40nm: Materials, Processes, and Structures

Ha, Daewon; Kim, Kinam

doi:10.1149/1.2911528

Cited by 2 publications

(1 citation statement)

References 6 publications

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“…With double patterning technologies enabling scalability to sub-40 nm [38], the ultimate viability of a FG or CT device as a memory cell may be dictated by the reduction of the number of stored charges. This is critical especially in a MLC technology and even more so for CT devices [39].…”

Section: Addressing Inter-cell Constraintsmentioning

confidence: 99%

The Flash Memory Cell for the Nodes to Come: Material Requirements from a Device Perspective

Govoreanu

Kittl

Vos³

et al. 2009

ECS Trans.

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The quest for mass storage and the diversity of end-user applications led to an aggressive scaling of the NAND Flash memory. A key factor to its success is the high density integration potential, which allows fabrication of large memory arrays. Reduction of the feature size below 40 nm may, however, require modifications of the conventional floating gate cell architecture, due to lack of physical space between neighboring cells, which no longer allows wrapping of the control gate over the floating gate. This has consequences on both intra- as well as inter-cell levels, calling for the introduction of high-k dielectrics in Flash memory. In this paper, we take a top-down stance and translate device characteristics into material requirements and/or points of attention that need to be addressed in order to ensure a successful continued scaling of the Flash memory for the upcoming technology generations.

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Section: Addressing Inter-cell Constraintsmentioning

confidence: 99%