Memory Mapped SPM: Protecting Instruction Scratchpad Memory in Embedded Systems against Soft Errors

Farbeh, Hamed; Fazeli, Mahdi; Khosravi, Faramarz; Miremadi, Seyed Ghassem

doi:10.1109/edcc.2012.13

Cited by 7 publications

(3 citation statements)

References 23 publications

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“…To calculate the Rate parameter, some stats file information and mathematical analysis are used. This calculation process has been shown in (2) and 3x = dbu × tbc tbt ,…”

Section: Experimental System Setupmentioning

confidence: 99%

“…Consumer electronics to industrial equipment, entertainment devices to academic equipment, and medical instruments to weapons and aerospace control systems, to name a few, are examples of embedded systems [1]. It is noteworthy that these systems are real‐time, in which timeliness is a must and missing the deadlines may result in a catastrophic consequence [2, 3].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

High performance and predictable memory controller for multicore mixed‐criticality real‐time systems

Dabaghi¹,

Farbeh²

2019

IET Computers & Digital Techniques

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Multicore processors are widely used in today's real-time embedded systems to satisfy the performance and predictability requirements as well as reduce cost. A vast majority of multicore embedded systems are running several tasks with mixed-criticality, in which the non-functional requirements of the tasks are different or even conflicting. A major challenge in mixed-criticality systems is to maximise the efficiency of shared resources while satisfying the criticality requirements. Shared memory is a key component that should be well managed and memory controller plays the main role in this case. Several memory controllers have been introduced in the literature for multicore processors. In this article, the authors performed a deep investigation on three state-of-the-art memory controllers using gem5 full-system simulator and Xilinx ISE Design Suite, and compared them in terms of predictability and performance. Then, the authors proposed a memory controller that provides the same predictability as the most predictable existing controller while improving the performance by 12.3%.

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“…To calculate the Rate parameter, some stats file information and mathematical analysis are used. This calculation process has been shown in (2) and 3x = dbu × tbc tbt ,…”

Section: Experimental System Setupmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

High performance and predictable memory controller for multicore mixed‐criticality real‐time systems

Dabaghi¹,

Farbeh²

2019

IET Computers & Digital Techniques

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show abstract

“…Reference [4] uses a parity code to error detection and a data duplication method to error correction. Reference [5] proposes 2-bit interleaved-parity per word to error detection. Reference [6] proposes the Partially Protected Caches (PPC) architec- hatayama@lab3.kuis.kyoto-u.ac.jp ture in which ECC is applied to a part of the cache.…”

Section: Introductionmentioning

confidence: 99%

An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems

Takuya

Takase

Takagi

et al. 2015

IPSJ Transactions on System LSI Design Methodology

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In this paper, we propose the use of a memory system which has a partially reliable scratch-pad memory (SPM). The reliable region of the SPM employing the ECC is higher soft error tolerant but larger energy consumption than the normal region. We propose an allocation method in order to optimize energy consumption while ensuring required reliability. An allocation method about instruction and data to proposed memory system is formulated as integer linear programming, where the solution archives optimal energy consumption and required reliability. Evaluation result shows that the proposed method is effective when overhead for error correction is large.

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A data recomputation approach for reliability improvement of scratchpad memory in embedded systems

Sayadi

Farbeh

Monazzah

et al. 2014

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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Memory Mapped SPM: Protecting Instruction Scratchpad Memory in Embedded Systems against Soft Errors

Cited by 7 publications

References 23 publications

High performance and predictable memory controller for multicore mixed‐criticality real‐time systems

High performance and predictable memory controller for multicore mixed‐criticality real‐time systems

An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems

A data recomputation approach for reliability improvement of scratchpad memory in embedded systems

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