A data recomputation approach for reliability improvement of scratchpad memory in embedded systems

Sayadi, Hossein; Farbeh, Hamed; Monazzah, Amir Mahdi Hosseini; Miremadi, Seyed Ghassem

doi:10.1109/dft.2014.6962091

Cited by 15 publications

(3 citation statements)

References 14 publications

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“…During the initialization state, dataset is divided into four separate subdatasets via Quarter function. then A kd-tree is generated for each sub-dataset, and the Lloyd function is employed for choosing initial centroids [3,25,29]. The most important part of this algorithm is the parallelism in tree traversal (Line 8-14), where each Cortex-A53 core is made responsible for transceiving data to/from PL in order to calculate and update its corresponding kd-tree characteristics (i.e.…”

Section: Parallelism In Kd-tree Traversalmentioning

confidence: 99%

Using Multi-Core HW/SW Co-design Architecture for Accelerating K-means Clustering Algorithm

Kamali

2018

Preprint

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The capability of classifying and clustering a desired set of data is an essential part of building knowledge from data. However, as the size and dimensionality of input data increases, the run-time for such clustering algorithms is expected to grow superlinearly, making it a big challenge when dealing with BigData.K-mean clustering is an essential tool for many big data applications including data mining, predictive analysis, forecasting studies, and machine learning. However, due to large size (volume) of Big-Data, and large dimensionality of its data points, even the application of a simple k-mean clustering may become extremely time and resource demanding. Specially when it is necessary to have a fast and modular dataset analysis flow.In this paper, we demonstrate that using a two-level filtering algorithm based on binary kd-tree structure is able to decrease the time of convergence in K-means algorithm for large datasets. The two-level filtering algorithm based on binary kd-tree structure evolves the SW to naturally divide the classification into smaller data sets, based on the number of available cores and size of logic available in a target FPGA. The empirical result on this two-level structure over multi-core FPGA-based architecture provides 330× speed-up compared to a conventional software-only solution.

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Section: Parallelism In Kd-tree Traversalmentioning

confidence: 99%

Using Multi-Core HW/SW Co-design Architecture for Accelerating K-means Clustering Algorithm

Kamali

2018

Preprint

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“…The work in [35] mainly focuses on page table and virtual memory optimization of big data and [5] presents the characterization of cache hierarchy for a Hadoop cluster. Few works [36], [37], [38] studied the impact of fault tolerant techniques on the performance and memory usage of embedded system. These works do not analyze the memory subsystem.…”

Section: Related Workmentioning

confidence: 99%

Storage and Memory Characterization of Data Intensive Workloads for Bare Metal Cloud

Makrani¹

2018

Preprint

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As the cost-per-byte of storage systems dramatically decreases, SSDs are finding their ways in emerging cloud infrastructure. Similar trend is happening for main memory subsystem, as advanced DRAM technologies with higher capacity, frequency and number of channels are deploying for cloud-scale solutions specially for non-virtualized environment where cloud subscribers can exactly specify the configuration of underling hardware. Given the performance sensitivity of standard workloads to the memory hierarchy parameters, it is important to understand the role of memory and storage for data intensive workloads. In this paper, we investigate how the choice of DRAM (high-end vs low-end) impacts the performance of Hadoop, Spark, and MPI based Big Data workloads in the presence of different storage types on bare metal cloud. Through a methodical experimental setup, we have analyzed the impact of DRAM capacity, operating frequency, the number of channels, storage type, and scale-out factors on the performance of these popular frameworks. Based on micro-architectural analysis, we classified data-intensive workloads into three groups namely I/O bound, compute bound, and memory bound. The characterization results show that neither DRAM capacity, frequency, nor the number of channels play a significant role on the performance of all studied Hadoop workloads as they are mostly I/O bound. On the other hand, our results reveal that iterative tasks (e.g. machine learning) in Spark and MPI are benefiting from a highend DRAM in particular high frequency and large number of channels, as they are memory or compute bound. Our results show that using SSD PCIe cannot shift the bottleneck from storage to memory, while it can change the workload behavior from I/O bound to compute bound.

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“…Consumer electronics to industrial equipment, entertainment devices to academic equipment, and medical instruments to weapons and aerospace control systems, to name a few, are examples of embedded systems [1]. It is noteworthy that these systems are real‐time, in which timeliness is a must and missing the deadlines may result in a catastrophic consequence [2, 3].…”

Section: Introductionmentioning

confidence: 99%

High performance and predictable memory controller for multicore mixed‐criticality real‐time systems

Dabaghi¹,

Farbeh²

2019

IET Computers & Digital Techniques

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Multicore processors are widely used in today's real-time embedded systems to satisfy the performance and predictability requirements as well as reduce cost. A vast majority of multicore embedded systems are running several tasks with mixed-criticality, in which the non-functional requirements of the tasks are different or even conflicting. A major challenge in mixed-criticality systems is to maximise the efficiency of shared resources while satisfying the criticality requirements. Shared memory is a key component that should be well managed and memory controller plays the main role in this case. Several memory controllers have been introduced in the literature for multicore processors. In this article, the authors performed a deep investigation on three state-of-the-art memory controllers using gem5 full-system simulator and Xilinx ISE Design Suite, and compared them in terms of predictability and performance. Then, the authors proposed a memory controller that provides the same predictability as the most predictable existing controller while improving the performance by 12.3%.

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A data recomputation approach for reliability improvement of scratchpad memory in embedded systems

Cited by 15 publications

References 14 publications

Using Multi-Core HW/SW Co-design Architecture for Accelerating K-means Clustering Algorithm

Using Multi-Core HW/SW Co-design Architecture for Accelerating K-means Clustering Algorithm

Storage and Memory Characterization of Data Intensive Workloads for Bare Metal Cloud

High performance and predictable memory controller for multicore mixed‐criticality real‐time systems

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