Memory efficient IFFT design for OFDM-based applications

Abstract

In this paper, we propose a new memory efficient IFFT design method for OFDM-based applications, based on a signed integer mapping of three IFFT input signals which are composed of modulated data, pilot and null signals. The proposed method focuses on reducing the word size of memory in the first two stages of the single-path delay feedback (SDF) IFFT architectures since the first two stages require 75% of the overall memory. By Synopsys simulation of the first two stages of IFFT, it is shown that the proposed method achieves about 40% reduction in area and 44% reduction in power consumption compared with the previous work.

Memory efficient DIT-based SDF IFFT for OFDM systems

“…The word-length reduction approach in [5] can only reduce the memory sizes at stages 1 and 2. However, if the bit-reversal part is located before stage 1 as shown in Fig.…”

“…3.1 2 2l -point DIT-based SDF IFFT architecture 2 2l -point radix-2 2 DIT-based SDF IFFT architectures satisfy the restriction and consequently the technique in [5] can be directly applied. As an example of memory reduction, in 64-QAM scheme, modulated signals have a word-length of 4-bits.…”

“…The memory reduction technique in [5] cannot be directly applied since complex multiplications exist between stages 1 and 2. For stages 1 and 2, only a group of 8 signals are added, subtracted or multiplied as dashed line in Fig.…”

“…By the algorithm, multiplications are moved after stage 2. Thus, the technique in [5] can be applied to DIT-based SDF IFFT architecture.…”

“…In [5], a signed integer mapping with a simple postprocessing was proposed to further reduce the memory size of IFFT. However, the approaches in [4,5] cannot be used to reduce the memory size in the bit-reversal part.…”