Memory-Efficient High-Speed Implementation of Kyber on Cortex-M4

Botros, Leon; Kannwischer, Matthias J.; Schwabe, Peter

doi:10.1007/978-3-030-23696-0_11

Cited by 73 publications

(50 citation statements)

References 16 publications

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“…al. in [11] indicate that even further improvements are possible with platform specific optimizations for Kyber.…”

Section: Key Exchangementioning

confidence: 99%

“…[19] presents an implementation of the standard lattice-based encryption scheme, proposed by Lindner and Peikert. In [11], the authors report performance measurements of an optimized software implementation of Kyber on a Cortex-M4 processor. The EU Horizon 2020 project SAFEcrypto also investigates the use of (standard) lattice-based cryptography in hardware, specifically for conservative use cases such as satellite communications.…”

Section: Pqc On Embeddedmentioning

confidence: 99%

See 1 more Smart Citation

Post-Quantum TLS on Embedded Systems: Integrating and Evaluating Kyber and SPHINCS+ with mbed TLS

Bürstinghaus-Steinbach

Krauß

Niederhagen

et al. 2020

Proceedings of the 15th ACM Asia Conference on Computer and Communications Security

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We present our integration of post-quantum cryptography (PQC), more specifically of the post-quantum KEM scheme Kyber for key establishment and the post-quantum signature scheme SPHINCS + , into the embedded TLS library mbed TLS. We measure the performance of these post-quantum primitives on four different embedded platforms with three different ARM processors and an Xtensa LX6 processor. Furthermore, we compare the performance of our experimental PQC cipher suite to a classical TLS variant using elliptic curve cryptography (ECC). Post-quantum key establishment and signature schemes have been either integrated into TLS or ported to embedded devices before. However, to the best of our knowledge, we are the first to combine TLS, post-quantum schemes, and embedded systems and to measure and evaluate the performance of post-quantum TLS on embedded platforms. Our results show that post-quantum key establishment with Kyber performs well in TLS on embedded devices compared to ECC variants. The use of SPHINCS + signatures comes with certain challenges in terms of signature size and signing time, which mainly affects the use of embedded systems as PQC-TLS server but does not necessarily prevent embedded systems to act as PQC-TLS clients. CCS CONCEPTS • Security and privacy → Digital signatures; • Networks → Transport protocols; Security protocols; • Theory of computation → Cryptographic primitives; Cryptographic protocols.

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“…al. in [11] indicate that even further improvements are possible with platform specific optimizations for Kyber.…”

Section: Key Exchangementioning

confidence: 99%

Section: Pqc On Embeddedmentioning

confidence: 99%

Post-Quantum TLS on Embedded Systems: Integrating and Evaluating Kyber and SPHINCS+ with mbed TLS

Bürstinghaus-Steinbach

Krauß

Niederhagen

et al. 2020

Proceedings of the 15th ACM Asia Conference on Computer and Communications Security

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“…In [KRSS19], the authors report that the cycles spent for hash computations are for the optimized NewHope and Kyber implementations on ARM Cortex-M4 between 60 % and 73 % of the total cycle count and for the Saber implementations between 40 % and 57 %. In [BKS19], the authors report that for their Kyber implementations even between 64 % and 81 % of the total cycle count is required for hash computations.…”

Section: Performance Bottlenecksmentioning

confidence: 99%

RISQ-V: Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography

Fritzmann

Sigl

Sepúlveda

2020

TCHES

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Empowering electronic devices to support Post-Quantum Cryptography (PQC) is a challenging task. PQC introduces new mathematical elements and operations which are usually not easy to implement on standard processors. Especially for low cost and resource constraint devices, hardware acceleration is usually required. In addition, as the standardization process of PQC is still ongoing, a focus on maintaining flexibility is mandatory. To cope with such requirements, hardware/software co-design techniques have been recently used for developing complex and highly customized PQC solutions. However, while most of the previous works have developed loosely coupled PQC accelerators, the design of tightly coupled accelerators and Instruction Set Architecture (ISA) extensions for PQC have been barely explored. To this end, we present RISQ-V, an enhanced RISC-V architecture that integrates a set of powerful tightly coupled accelerators to speed up lattice-based PQC. RISQ-V efficiently reuses processor resources and reduces the amount of memory accesses. This significantly increases the performance while keeping the silicon area overhead low. We present three contributions. First, we propose a set of powerful hardware accelerators deeply integrated into the RISC-V pipeline. Second, we extended the RISC-V ISA with 29 new instructions to efficiently perform operations for lattice-based cryptography. Third, we implemented our RISQ-V in ASIC technology and on FPGA. We evaluated the performance of NewHope, Kyber, and Saber on RISQ-V. Compared to the pure software implementation on RISC-V, our co-design implementations show a speedup factor of up to 11.4 for NewHope, 9.6 for Kyber, and 2.7 for Saber. For the ASIC implementation, the energy consumption was reduced by factors of up to 9.5 for NewHope, 7.7 for Kyber, and 2.1 for Saber. The cell count of the CPU was increased by a factor of 1.6 compared to the original RISC-V design, which can be considered as a moderate increase for the achieved performance gain.

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“…This implementation also solves the storage issue of polynomials by using BRAM inside the module. Table II compares the performance of this work with the performances of the original reference implementations on Intel Core i7-4770K (Haswell) by C language [5] and on Cortex-M4 in 24MHz [6]. With a variety of performance optimizations in hardware implementations, the amount of total clock cycles for both encryption and decryption of this propsed design reduces notably compared with Cortex-M4 implementation as well as Haswell implementation.…”

Section: Ntt Modulementioning

confidence: 99%

“…The hardware logic is connected to the ARM processor on the Zynq platform through the AXI bus. As for the PQC CRYSTALS-KYBER (Kyber) [5] algorithm version 2.0, the work in [6] presented an implementation on ARM Cortex-M4 embedded processor. It was able to achieve 18% performance speedup while using a tiny memory footprint.…”

Section: Introductionmentioning

confidence: 99%

A pure hardware implementation of CRYSTALS-KYBER PQC algorithm through resource reuse

Huang

Lei

et al. 2020

IEICE Electron. Express

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This paper presents a pure hardware implementation of CRYSTALS-KYBER algorithm on Xilinx FPGAs. CRYSTALS-KYBER is one of 26 candidate algorithms in Round 2 of NIST Post-Quantum Cryptography (PQC) standardization process. The proposed design focuses on maximizing resource utilization by reusing most of the functional modules in the encapsulation and decapsulation processes of the algorithm. For instance, the hash module integrates several different hash functions in one module. Efficient parallel and pipelined computations are applied in the NTT module. Through the analysis of simulation and synthesis results, it is found that the proposed work has the advantages of higher frequencies and lower execution times. The scheme operates at 155 MHz and 192 MHz frequencies on Xilinx Artix-7 and Virtex-7 FPGAs, respectively. Compared with the performance of an embedded Cortex-M4 processor, the hardware implementation can achieve a maximum speedup of 129 times for encryption/decryption.

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Memory-Efficient High-Speed Implementation of Kyber on Cortex-M4

Cited by 73 publications

References 16 publications

Post-Quantum TLS on Embedded Systems: Integrating and Evaluating Kyber and SPHINCS+ with mbed TLS

Post-Quantum TLS on Embedded Systems: Integrating and Evaluating Kyber and SPHINCS+ with mbed TLS

RISQ-V: Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography

A pure hardware implementation of CRYSTALS-KYBER PQC algorithm through resource reuse

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