A pure hardware implementation of CRYSTALS-KYBER PQC algorithm through resource reuse

Abstract

This paper presents a pure hardware implementation of CRYSTALS-KYBER algorithm on Xilinx FPGAs. CRYSTALS-KYBER is one of 26 candidate algorithms in Round 2 of NIST Post-Quantum Cryptography (PQC) standardization process. The proposed design focuses on maximizing resource utilization by reusing most of the functional modules in the encapsulation and decapsulation processes of the algorithm. For instance, the hash module integrates several different hash functions in one module. Efficient parallel and pipelined computations are applied in the NTT module. Through the analysis of simulation and synthesis results, it is found that the proposed work has the advantages of higher frequencies and lower execution times. The scheme operates at 155 MHz and 192 MHz frequencies on Xilinx Artix-7 and Virtex-7 FPGAs, respectively. Compared with the performance of an embedded Cortex-M4 processor, the hardware implementation can achieve a maximum speedup of 129 times for encryption/decryption.

A Compact Hardware Implementation of CCA-Secure Key Exchange Mechanism CRYSTALS-KYBER on FPGA

“…As the contest progresses to the third round, and is expected to last 12-18 months from July 2020, more dedicated designs would better demonstrate the strength and illustrate the intrinsic property of a certain protocol, fitting the expectation from NIST that more performance data of seven finalists and eight alternate candidates for hardware implementation would emerge [AASA + 20]. A few published ones that reported results for Kyber are [DFA + 20] and [HHLW20]. Moreover, some procedures that are intractable to handle in hardware but shared among different participants in the contest, can be properly designed once and used in a similarly way among corresponding protocols, especially tasks required by the Fujisaki-Okamoto transform in re-encryption phase.…”

“…Both [DFA + 20] and[HHLW20] report performance and resource consumption of standalone hardware implementation of Kyber. In [DFA + 20], besides summarizing and analyzing massive results reported by other groups, four CCA-secure KEM candidates of the second round are implemented in pure hardware as the authors report, including Kyber.…”

“…4× of DSPs, 5× of BRAMs as well as 1.5× LUTs are involved, implying more computational cores participate in calculation and total cycle counts would decrease. In[HHLW20], BRAMs are inserted between different modules for communication, and bottom modules are reused in realizing related upper functionalities extensively. Through elaborate scheduling with limited computational resources, cycle counts of our design is 10 times smaller than that of[HHLW20], and resource consumption corresponding to LUT and FF are more than 10× and nearly 40× smaller as well.…”

Towards CRYSTALS-Kyber VHDL Implementation

“…Even if some Kyber RTL-based designs are now available, there is still a lack of its optimized implementation on FPGA. A Verilog Kyber implementation on Xilinx Artix-7 and Virtex-7 FPGAs is presented in (Huang et al, 2020). The article stays on a high level description of Kyber and no NTT and Keccak results are shown.…”

A System-on-a-Chip Implementation of a Post-Quantum Cryptography Scheme for Smart Meter Data Communications

“…On the other hand, ref. [ 18 ] presented a pure hardware implementation of the CRYSTALS-Kyber scheme using Field Programmable Gate Array (FPGA) focusing on high performance. Note that these aforementioned solutions are note suitable for SM systems because they are based on high-end platforms.…”