Memory efficient design of an MPEG-4 video encoder for FPGAs

Abstract

The improving resolutions of new video appliances continuously increase the throughput requirements of video codecs and complicate the challenges encountered during their cost-efficient design. We propose an FPGA implementation of a high-performance MPEG-4 video encoder. The fully dedicated video pipeline is realized using a systematic design approach and exploits the inherent functional parallelism of the compression algorithm. The effect of memory and algorithmic optimizations applied at the high-level are measured on the RTL description. The resulting MPEG-4 video encoder efficiently uses the FPGA blockRAMs, uses burst oriented accesses to external memory and supports real-time processing of 30 4CIF frames per second.

A software/hardware platform for rapid prototyping of video and multimedia designs

“…As described in [2], this debug step was used after the VHDL design was verified in the ModelSim simulator [11]. It proved to be an invaluable debug step, not just for verifying actual FPGA hardware, but providing a "bursty" data transfer environment to strain the communication primitives in the design.…”

“…Therefore, the generic and non-optimized software description has also become the starting point for any implementation activity of the standard. Unfortunately, working and reasoning on architectural solutions or on appropriate software/hardware (SW/HW) partitioning on several tens of thousands of lines is a very time-and resource-consuming task [2]. In the traditional way of designing HW blocks, the full rewriting of the reference software to isolate candidate HW blocks and architectures and to generate appropriate test vectors for the correct elicitation of the designed HW system are mandatory tasks that could result in even more resource-demanding tasks than the HW design itself.…”

Muir Hardware Synthesis for Multimedia Applications

“…The image is subdivided into 16x16 pixel Macroblocks (MBs), for each of which Motion Vectors (MVs) are calculated in the Motion Estimation (ME) block, indicating the movement of the MB between frames. This is the most computationally demanding [11] part of the application. The MVs are encoded into the output bitstream.…”

Performance-Complexity Analysis of High Resolution Video Encoder and its Memory Organization for DSP Implementation

“…VLSI technology is a solution for such computationally intensive development, e.g. some VGA resolution (640x480) encoders have been implemented based on FPGA [3] [4]. Under VLSI architecture, particular algorithms can be highly optimized since hardware is directly designed, but the disadvantage of the approach is the limited adaptability which always results in a redesign.…”