2006 IEEE International Conference on Multimedia and Expo 2006
DOI: 10.1109/icme.2006.262767
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Performance-Complexity Analysis of High Resolution Video Encoder and its Memory Organization for DSP Implementation

Abstract: This paper first analyses the relationship between performance and complexity of several state-of-the-art coding algorithms for high resolution videos. Based on the coding efficiency comparison under different config parameters and the intra mode usage in P/B frame, this paper presents a practical scheme to improve the coding speed with slight quality loss. And a DSP-oriented two-level internal memory organization is also proposed to keep pipeline processing. In such organization, block correlation caused by m… Show more

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Cited by 7 publications
(1 citation statement)
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“…As the experimental results have shown that two fixed-size block levels are generally good for video coding [31] and video deinterlacing [16], we propose a three-leveled block strategy that has two fixed-size block levels and one variable-size block level to achieve better prediction and motion compensation. In this paper, a motion-compensated deinterlacing scheme is presented based on hierarchical motion analysis, which is incarnated by the novel three-leveled block strategy.…”
mentioning
confidence: 99%
“…As the experimental results have shown that two fixed-size block levels are generally good for video coding [31] and video deinterlacing [16], we propose a three-leveled block strategy that has two fixed-size block levels and one variable-size block level to achieve better prediction and motion compensation. In this paper, a motion-compensated deinterlacing scheme is presented based on hierarchical motion analysis, which is incarnated by the novel three-leveled block strategy.…”
mentioning
confidence: 99%