Memory Conflict Analysis and Interleaver Design for Parallel Turbo Decoding Supporting HSPA Evolution

Asghar, Rizwan; Wu, Di; Eilert, Johan; Liu, Dake

doi:10.1109/dsd.2009.178

Cited by 8 publications

(9 citation statements)

References 16 publications

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“…Many research papers proposed on-the-fly IAG hardware implementations [6,7,8,9,10,11]. However, most of them focused on non-parallel interleaver architectures.…”

Section: A Reducing Memory Usage For Interleaving Address Generationmentioning

confidence: 99%

“…Only [5] and our work support both interleaver and deinterleaver dual-mode. The architecture in [10] can support a parallel turbo decoder with different block sizes, but the architecture is limited to turbo decoders with low parallelism. This comparison shows that the proposed architecture has good hardware efficiency, great flexibility and good configurability.…”

Section: Comparisonmentioning

confidence: 99%

See 1 more Smart Citation

Parallel interleaver architecture with new scheduling scheme for high throughput configurable turbo decoder

Wang

Vosoughi

Shen

et al. 2013

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

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Abstract-Parallel architecture is required for high throughput turbo decoder to meet the data rate requirements of the emerging wireless communication systems. However, due to the severe memory conflict problem caused by parallel architectures, the interleaver design has become a major challenge that limits the achievable throughput. Moreover, the high complexity of the interleaver algorithm makes the parallel interleaving address generation hardware very difficult to implement. In this paper, we propose a parallel interleaver architecture that can generate multiple interleaving addresses on-the-fly. We devised a novel scheduling scheme with which we can use more efficient buffer structures to eliminate memory contention. The synthesis results show that the proposed architecture with the new scheduling scheme can significantly reduce memory usage and hardware complexity. The proposed architecture also shows great flexibility and scalability compared to prior work.

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“…Many research papers proposed on-the-fly IAG hardware implementations [6,7,8,9,10,11]. However, most of them focused on non-parallel interleaver architectures.…”

Section: A Reducing Memory Usage For Interleaving Address Generationmentioning

confidence: 99%

Section: Comparisonmentioning

confidence: 99%

Parallel interleaver architecture with new scheduling scheme for high throughput configurable turbo decoder

Wang

Vosoughi

Shen

et al. 2013

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

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“…Steps (1)--(4), (6), and (7) are exactly equivalent to the standard algorithm [1]. Steps (5), (8), (10), and (11) in particular include the main contribution of our proposed algorithm (these steps are boldface in the text).…”

Section: Proposed Algorithm For Umts/hspa+ Interleaved Address Gmentioning

confidence: 99%

“…The previously proposed on-the-fly UMTS interleavers [5], [6], [9]-- [12] are designed to be used in parallel turbo decoders with conventional scheduling, where reading is done in an interleaved fashion. In these methods, when the bth interleaved data must be read, the original address of b is computed and used for reading.…”

Section: Introductionmentioning

confidence: 99%

Highly scalable on-the-fly interleaved address generation for UMTS/HSPA+ parallel turbo decoder

Vosoughi

Wang

Shen

et al. 2013

2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors

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Abstract-High throughput parallel interleaver design is a major challenge in designing parallel turbo decoders that conform to high data rate requirements of advanced standards such as HSPA+. The hardware complexity of the HSPA+ interleaver makes it difficult to scale to high degrees of parallelism. We propose a novel algorithm and architecture for on-the-fly parallel interleaved address generation in UMTS/HSPA+ standard that is highly scalable. Our proposed algorithm generates an interleaved memory address from an original input address without building the complete interleaving pattern or storing it; the generated interleaved address can be used directly for interleaved writing to memory blocks. We use an extended Euclidean algorithm for modular multiplicative inversion as a step towards reversed intra-row permutations in UMTS/HSPA+ standard. As a result, we can determine interleaved addresses from original addresses. We also propose an efficient and scalable hardware architecture for our method. Our design generates 32 interleaved addresses in one cycle and satisfies the data rate requirement of 672 Mbps in HSPA+ while the silicon area and frequency is improved compared to recent related works.

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“…The work presented in [14] − [19] covers single address generation supporting maximum of two standards but they do not support parallel interleaver address generation. Reference [21] provides a parallel interleaver architecture for HSPA+ but it does not cover the support for multi-mode environment. A good analysis of memory conflicts for interleaver in turbo decoder is provided in [22].…”

Section: Background and Challengesmentioning

confidence: 99%

Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding

Asghar

Eilert

et al. 2009

J Sign Process Syst Sign Image Video Technol

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Abstract − This paper presents a novel hardware interleaver architecture for unified parallel turbo decoding. The architecture is fully re-configurable among multiple standards like HSPA Evolution, DVB-SH, 3GPP-LTE and WiMAX. Turbo codes being widely used for error correction in today's consumer electronics are prone to introduce higher latency due to bigger block sizes and multiple iterations. Many parallel turbo decoding architectures have recently been proposed to enhance the channel throughput but the interleaving algorithms used in different standards do not freely allow using them due to higher percentage of memory conflicts. The architecture presented in this paper provides a re-configurable platform for implementing the parallel interleavers for different standards by managing the conflicts involved in each. The memory conflicts are managed by applying different approaches like stream misalignment, memory division and use of small FIFO buffer. The proposed flexible architecture is low cost and consumes 0.085 mm 2 area in 65nm CMOS process. It can implement up to 8 parallel interleavers and can operate at a frequency of 200 MHz, thus providing significant support to higher throughput systems based on parallel SISO processors.

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Memory Conflict Analysis and Interleaver Design for Parallel Turbo Decoding Supporting HSPA Evolution

Cited by 8 publications

References 16 publications

Parallel interleaver architecture with new scheduling scheme for high throughput configurable turbo decoder

Parallel interleaver architecture with new scheduling scheme for high throughput configurable turbo decoder

Highly scalable on-the-fly interleaved address generation for UMTS/HSPA+ parallel turbo decoder

Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding

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Memory Conflict Analysis and Interleaver Design for Parallel Turbo Decoding Supporting HSPA Evolution

Cited by 8 publications

References 16 publications

Parallel interleaver architecture with new scheduling scheme for high throughput configurable turbo decoder

Parallel interleaver architecture with new scheduling scheme for high throughput configurable turbo decoder

Highly scalable on-the-fly interleaved address generation for UMTS/HSPA&#x002B; parallel turbo decoder

Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding

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Highly scalable on-the-fly interleaved address generation for UMTS/HSPA+ parallel turbo decoder