2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors 2013
DOI: 10.1109/asap.2013.6567601
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Highly scalable on-the-fly interleaved address generation for UMTS/HSPA+ parallel turbo decoder

Abstract: Abstract-High throughput parallel interleaver design is a major challenge in designing parallel turbo decoders that conform to high data rate requirements of advanced standards such as HSPA+. The hardware complexity of the HSPA+ interleaver makes it difficult to scale to high degrees of parallelism. We propose a novel algorithm and architecture for on-the-fly parallel interleaved address generation in UMTS/HSPA+ standard that is highly scalable. Our proposed algorithm generates an interleaved memory address fr… Show more

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Cited by 4 publications
(3 citation statements)
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“…They propose a new algorithm and architecture for the highly scalable UMTS/HSPA+ standard's on-the-fly generation of parallel interleaved addresses [36].…”
Section: Vosoug Hi Et Al (2013)mentioning
confidence: 99%
“…They propose a new algorithm and architecture for the highly scalable UMTS/HSPA+ standard's on-the-fly generation of parallel interleaved addresses [36].…”
Section: Vosoug Hi Et Al (2013)mentioning
confidence: 99%
“…The core operation of the HSPA+ interleaver can be summarized as computing a column index function U i (j) from the original column j after intra-row permutation j → U i (j) for the i-th row, using the formula U i (j) = s((j × r i ) mod (P − 1)). Similarly, it has been proved that the core operation in the UMTS/HSPA+ deinterleaver is to compute an intra-row permutation j → U −1 i (j ) using formula U −1 i (j ) = (s −1 (j )×m i ) mod (P −1) [40]. The core computation units in the interleaver and deinterleaver can be summarized as the same computation kernel (a × b) mod c. Furthermore, most of the intermediate values precomputed by the pre-processing units can be reused, except for only a few intermediate values used exclusively by the deinterleaver mode.…”
Section: Efficient Unified Interleaver/deinterleaver Architecturementioning
confidence: 99%
“…Here, let us take the column-row random interleaving algorithm in the HSPA+ standard as an example to explain how these blocks work. The algorithm details and notation definitions can be found from 3GPP UMTS/HSPA+ standards [2] or references [22], [40]. The preset parameter storage implemented using ROMs contains static parameters such as interrow permutation pattern T i (128×5bit tROM) and permutated sequence r i (1440 × 7bit rROM) used by both modes, and the modular multiplicative inverse sequence m i (1200 × 7bit mROM) used exclusively by the deinterleaver [40].…”
Section: Efficient Unified Interleaver/deinterleaver Architecturementioning
confidence: 99%