HSPA&amp;#x003B;/LTE-A turbo decoder on GPU and multicore CPU

Wu, Michael; Wang, Guohui; Yin, Bei; Studer, Christoph; Cavallaro, Joseph R.

doi:10.1109/acssc.2013.6810402

Cited by 15 publications

(11 citation statements)

References 10 publications

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“…In the literature, intra-frame parallelism is often mapped on SIMD units while inter-frame parallelization is usually kept for multithreaded approaches (SPMD). In [16], [20], multiple trellisstate computations are performed in parallel in the SIMD units. In [9]- [18], [20], the decoded frame is split into sub-blocks that are processed in parallel in the SIMD units.…”

Section: Parallelism Analysismentioning

confidence: 99%

“…Thanks to a large set of processor cores it becomes possible to implement computation intensive applications such as channel decoding with a lower energy consumption in comparison to GPU targets. In [16], [19], [20], software turbo decoders are implemented on GPP targets with intra-frame parallelism, similar to hardware-oriented strategies. Unlike these works, we propose to investigate the exclusive use of inter-frame parallelism.…”

Section: Introductionmentioning

confidence: 99%

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Beyond Gbps Turbo decoder on multi-core CPUs

Cassagne

Tonnellier

Leroux

et al. 2016

2016 9th International Symposium on Turbo Codes and Iterative Information Processing (ISTC)

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This paper presents a high-throughput implementation of a portable software turbo decoder. The code is optimized for traditional multi-core CPUs (like x86) and it is based on the Enhanced max-log-MAP turbo decoding variant. The code follows the LTE-Advanced specification. The key of the high performance comes from an inter-frame SIMD strategy combined with a fixed-point representation. Our results show that proposed multi-core CPU implementation of turbo-decoders is a challenging alternative to GPU implementation in terms of throughput and energy efficiency. On a high-end processor, our software turbo-decoder exceeds 1 Gbps information throughput for all rate-1/3 LTE codes with K < 4096.

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Section: Parallelism Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Beyond Gbps Turbo decoder on multi-core CPUs

Cassagne

Tonnellier

Leroux

et al. 2016

2016 9th International Symposium on Turbo Codes and Iterative Information Processing (ISTC)

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show abstract

“…In this context of network virtualization, recent articles have proposed several optimized software decoders, corresponding to different channel codes : LDPC codes [16,17], polar codes [4,5,11,28], turbo codes [3,30,31]. All of these works show the possibility to reach a good level of performance by making extensive use of SIMD (Single Instruction Multiple Data) units.…”

Section: Introductionmentioning

confidence: 99%

Mipp

Cassagne

Aumage

Barthou

et al. 2018

Proceedings of the 2018 4th Workshop on Programming Models for SIMD/Vector Processing

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Error correction code (ECC) processing has so far been performed on dedicated hardware for previous generations of mobile communication standards, to meet latency and bandwidth constraints. As the 5G mobile standard, and its associated channel coding algorithms, are now being specified, modern CPUs are progressing to the point where software channel decoders can viably be contemplated. A key aspect in reaching this transition point is to get the most of CPUs SIMD units on the decoding algorithms being pondered for 5G mobile standards. The nature and diversity of such algorithms requires highly versatile programming tools. This paper demonstrates the virtues and versatility of our MIPP SIMD wrapper in implementing a high performance portfolio of key ECC decoding algorithms.

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“…In [2,3,4], GPUs are used to realize turbo decoding algorithm for their computing power and programmability. By fully utilizing the enormous parallelism of GPUs, many codeword blocks can be decoded simultaneously.…”

Section: Introductionmentioning

confidence: 99%

A multi-core-based heterogeneous parallel turbo decoder

Zeng

Zhang

et al. 2017

IEICE Electron. Express

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It has always been a challenging task to implement a turbo decoder because it's typically the most compute-intensive and time-consuming part in a wireless communication system. This becomes especially obvious when realizing a turbo decoder through CPUs or GPUs. In this paper, we present a heterogeneous and highly reconfigurable parallel turbo decoder for LTE by employing a multi-core processor platform. A modified sliding-window algorithm is proposed to fully exploit the parallelism of turbo decoder, and a SIMD hardware module is designed for the multi-core processor to accelerate the decoding process. Synthesized result in a 65-nm CMOS process shows that the whole system can run at a maximum clock frequency of 830 MHz, and a decoding throughput of 135 Mbps is achieved for a codeword block length of 6144 at 6 iterations. In addition, the speed-up rate compared to an unaccelerated implementation through the same multicore platform is in the order of 800%.

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HSPA;/LTE-A turbo decoder on GPU and multicore CPU

Cited by 15 publications

References 10 publications

Beyond Gbps Turbo decoder on multi-core CPUs

Beyond Gbps Turbo decoder on multi-core CPUs

Mipp

A multi-core-based heterogeneous parallel turbo decoder

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