Beyond Gbps Turbo decoder on multi-core CPUs

Cassagne, Adrien; Tonnellier, Thibaud; Leroux, Camille; Gal, Bertrand Le; Aumage, Olivier; Barthou, Denis

doi:10.1109/istc.2016.7593092

Cited by 13 publications

(6 citation statements)

References 19 publications

(29 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In order to study AVX impact on power and energy consumption, we target four different HPC applications, which have automatic vectorization (by setting a compilation flag or an environment variable). We used applications with different CPU behavior and/or available options: HPL 15 and Plasma svd 16 which use the Math Kernel Library (MKL), AFF3CT 17 and SToRM 18 . Note that AFF3CT and SToRM only use integer.…”

Section: Applicationsmentioning

confidence: 99%

Thermal design power and vectorized instructions behavior

Guermouche

Orgerie

2021

Concurrency and Computation

View full text Add to dashboard Cite

In this paper, we study and compare the impact of thermal design power and SIMD instructions on performance, power and energy consumption of processors and memory. The study is performed on three different architectures providing different characteristics and four applications with different profiles (including one application with different phases, each phase having a different profile).The study shows that, because of processor frequency, performance and power consumption are strongly related to thermal design power. It also shows that AVX512 has unexpected behavior regarding processor power consumption, while DRAM power consumption is impacted by SIMD instructions because of the generated memory throughput. Finally, this paper tackles the impact of turboboost which shows equivalent to better performance for all the studied cases while not always decreasing energy consumption.

show abstract

Section: Applicationsmentioning

confidence: 99%

Thermal design power and vectorized instructions behavior

Guermouche

Orgerie

2021

Concurrency and Computation

View full text Add to dashboard Cite

show abstract

“…and 4G LTE standards and may be candidates for the future 6G [38]. Their decoding algorithm consists of tracking/routing two mesh networks which are connected to a data interleaver [15], [39]. Fixed data widths of 8 or 16 bits are used.…”

Section: Ecc Decoding Algorithmsmentioning

confidence: 99%

Extended RISC-V hardware architecture for future digital communication systems

Tourres

Gal

Crenne

et al. 2021

2021 IEEE 4th 5G World Forum (5GWF)

Self Cite

View full text Add to dashboard Cite

HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L'archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

show abstract

“…It's obviously that the others suffer from problems of too low throughput or too high latency, or both. Take work in [5] for example, although an excellent decoding throughput has been achieved, the decoding latency is too long to be tolerated. We also can see that our design provides a trade-off between latency and throughput.…”

Section: Optimized Decoding Algorithmmentioning

confidence: 99%

“…By fully utilizing the enormous parallelism of GPUs, many codeword blocks can be decoded simultaneously. The work in [5] implements a turbo decoder by employing high-end CPUs. However, their implementations may suffer from some problems, either with too low throughput or too high latency.…”

Section: Introductionmentioning

confidence: 99%

A multi-core-based heterogeneous parallel turbo decoder

Zeng

Zhang

et al. 2017

IEICE Electron. Express

View full text Add to dashboard Cite

It has always been a challenging task to implement a turbo decoder because it's typically the most compute-intensive and time-consuming part in a wireless communication system. This becomes especially obvious when realizing a turbo decoder through CPUs or GPUs. In this paper, we present a heterogeneous and highly reconfigurable parallel turbo decoder for LTE by employing a multi-core processor platform. A modified sliding-window algorithm is proposed to fully exploit the parallelism of turbo decoder, and a SIMD hardware module is designed for the multi-core processor to accelerate the decoding process. Synthesized result in a 65-nm CMOS process shows that the whole system can run at a maximum clock frequency of 830 MHz, and a decoding throughput of 135 Mbps is achieved for a codeword block length of 6144 at 6 iterations. In addition, the speed-up rate compared to an unaccelerated implementation through the same multicore platform is in the order of 800%.

show abstract

Beyond Gbps Turbo decoder on multi-core CPUs

Cited by 13 publications

References 19 publications

Thermal design power and vectorized instructions behavior

Thermal design power and vectorized instructions behavior

Extended RISC-V hardware architecture for future digital communication systems

A multi-core-based heterogeneous parallel turbo decoder

Contact Info

Product

Resources

About