Memory built-in self-repair for nanotechnologies

Nicolaidis, M.; Achouri, N.; Anghel, Lorena

doi:10.1109/olt.2003.1214373

Cited by 13 publications

(5 citation statements)

References 11 publications

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“…A controller coordinates the spare resources allocation by receiving signals from the BIST circuitry regarding the localisation of the faulty part. Examples of such techniques can be seen in [7]- [15]. In [7], a columnbased approach is followed, using hardwired remapping of the spares.…”

Section: Introductionmentioning

confidence: 99%

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A BISR Architecture for Embedded Memories

Pekmestzi

Axelos

Sideris

et al. 2008

2008 14th IEEE International on-Line Testing Symposium

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In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities. On a 4Mbit memory and an average number of 1024 memory defects per IC, a repair ratio of 100% and over 90% require less than 2% and 1% memory overhead respectively.

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Section: Introductionmentioning

confidence: 99%

“…In [14] a FLASH programmable BIST/BISR scheme utilises spare columns for repairs. [15] suggests that a combination of techniques is more efficient on modern ICs where high defect densities are expected on first runs and proposes both static and dynamic data bin repair schemes that work towards rectifying that problem.…”

Section: Introductionmentioning

confidence: 99%

A BISR Architecture for Embedded Memories

Pekmestzi

Axelos

Sideris

et al. 2008

2008 14th IEEE International on-Line Testing Symposium

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“…In case of CAM hit, we apply both input data (21) and the new block address (8) to the memory. The largest hardware overhead incurred in this approach is due to the CAM (7).…”

Section: ) Address Reconfigurationmentioning

confidence: 99%

“…Moreover, the steps (12), (15), (16) and (19) can be easily implemented using combinational logic. We require only three registers to store the mapped address (8), data output (14) and new data (21). This scheme does not affect memory access time for a functional memory location.…”

Section: ) Address Reconfigurationmentioning

confidence: 99%

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A DFT Methodology for Repairing Embedded Memories of Large MPSoCs

Ganeshpure

Kundu

2012

2012 IEEE Computer Society Annual Symposium on VLSI

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Memory Built-In Self-Test (MBIST) is used to test large memories embedded in Multi-Processor System on Chip (MPSoC). With increase in memory size, memory repair becomes necessary to improve yield. Memory repair consists of complex offline analysis requiring (i) fault diagnosis and (ii) optimizing reconfiguration based on failure map and available spare resources. This paper presents an embedded repair scheme that uses resources within a MPSoC. The main challenge involves establishing integrity of such internal resources before they are used for repair. We propose a layered approach to testing that (i) tests local processor cache first and uses (ii) software based selftesting of limited processor functions using (iii) a small program loaded into a cache from tester, which then (iv) serves as a vehicle for memory repair. This repaired memory can store and run larger software-based self-test programs to test the remaining systems. Software simulation is used to demonstrate feasibility of the proposed DFT scheme and test methodology. The main advantages of this approach are (i) avoidance of memory testers that are typically necessary for memory repair, (ii) avoiding additional hardware to support repair by using existing resources and (iii) testing all components using a logic tester.

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System on a Chip (SoC) Test

Integrated Circuit Test Engineering

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Memory built-in self-repair for nanotechnologies

Cited by 13 publications

References 11 publications

A BISR Architecture for Embedded Memories

A BISR Architecture for Embedded Memories

A DFT Methodology for Repairing Embedded Memories of Large MPSoCs

System on a Chip (SoC) Test

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