Abstract:Abstract-We develop a framework for mechanized certification of secure hardware systems built out of commercial off-theshelf (COTS) components purchased from untrusted vendors. Certification requires a guarantee that the fabricated system satisfies the requisite safety and security properties. Our framework facilitates this by (1) providing an unambiguous description of the requirements specification in a formal, computational logic, (2) a formalized hardware description language (HDL) to describe the implemen… Show more
“…HOL theorem prover [21] has been used in several well-documented projects [13,23]. ACL2 is also used a lot in hardware verification [17,38,39,27,51,54,53]. Our project is however somewhat different from the traditional applications of theorem provers.…”
Section: Use Of Theorem Provers In Hardware Verifica-tionmentioning
Due to the rapidly increasing complexity in hardware designs and competitive time to market trends in the industry, there is an inherent need to move designs to a higher level of abstraction. Behavioral Synthesis is the process of automatically compiling such Electronic System Level (ESL) designs written in high-level languages such as C, C++ or SystemC into Register-Transfer Level (RTL) implementation in hardware description languages such as Verilog or VHDL. However, the adoption of this flow is dependent on designers' faith in the correctness of behavioral synthesis tools.Loop pipelining is a critical transformation employed in behavioral synthesis process, and ubiquitous in commercial and academic behavioral synthesis tools. It
“…HOL theorem prover [21] has been used in several well-documented projects [13,23]. ACL2 is also used a lot in hardware verification [17,38,39,27,51,54,53]. Our project is however somewhat different from the traditional applications of theorem provers.…”
Section: Use Of Theorem Provers In Hardware Verifica-tionmentioning
Due to the rapidly increasing complexity in hardware designs and competitive time to market trends in the industry, there is an inherent need to move designs to a higher level of abstraction. Behavioral Synthesis is the process of automatically compiling such Electronic System Level (ESL) designs written in high-level languages such as C, C++ or SystemC into Register-Transfer Level (RTL) implementation in hardware description languages such as Verilog or VHDL. However, the adoption of this flow is dependent on designers' faith in the correctness of behavioral synthesis tools.Loop pipelining is a critical transformation employed in behavioral synthesis process, and ubiquitous in commercial and academic behavioral synthesis tools. It
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