Mechanism of hot electron induced degradation in LDD NMOS-FET

Toyoshima, Y.; Nihira, H.; Wada, Masanori; Kanzaki, K.

doi:10.1109/iedm.1984.190844

Cited by 14 publications

(3 citation statements)

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“…T HE spacer-induced degradation resulting from hot-carrier injection is believed to be intrinsic to the conventional LDD structure with n -to-gate offset [1], [2]. In recent years, several improved drain-engineered MOSFET's, such as MLDD [3], ITLDD [4], GOLD [5], and LATID [6], have received much attention because of their abilities to enhance current drivability and alleviate spacer-induced degradation [2].…”

Section: Introductionmentioning

confidence: 99%

“…On the other hand, since interface state generation is the dominant mechanism responsible for the variation of the above characteristics, determination of the interface states, in particular its spatial distributions, becomes critical to a device engineering work. For example, the drain current degradations are closely related to the distribution of hot-carrier induced interface states and device parameters such as n doping profile and gate oxide thickness [1], [8]. Therefore, to get insight into the degradation process of drain-engineered device in more detail, it is essential to first physically characterize the interface state profile.…”

Section: Introductionmentioning

confidence: 99%

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A new approach for characterizing structure-dependent hot-carrier effects in drain-engineered MOSFET's

Chung

Yang

1999

IEEE Trans. Electron Devices

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In this paper, we have demonstrated successfully a new approach for evaluating the hot-carrier reliability in submicron LDD MOSFET with various drain engineering. It was developed based on an efficient charge pumping measurement technique along with a new criterion. This new criterion is based on an understanding of the interface state (N it) distribution, instead of substrate current or impact ionization rate, for evaluating the hot-carrier reliability of drain-engineered devices. The position of the peak N it distribution as well as the electric field distribution is critical to the device hot-carrier reliability. From the characterized N it spatial distribution, we found that the shape of the interface state distribution is similar to that of the electric field. Also, to suppress the spacer-induced degradation, we should keep the peak values of interface state away from the spacer region. In our studied example, for conventional LDD device, sidewall spacer is the dominant damaged region since the interface state in this region causes an additional series resistance which leads to drain current degradation. LATID device can effectively reduce hot-carrier effect since most of the interface states are generated away from the gate edge toward the channel region such that the spacer-induced resistance effect is weaker than that of LDD devices.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A new approach for characterizing structure-dependent hot-carrier effects in drain-engineered MOSFET's

Chung

Yang

1999

IEEE Trans. Electron Devices

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“…The "spacer-induced degradation" has also been found in LDD transistors fabricated with photoresist-masked implants without the oxide sidewall-spacer process [4], and is believed to be intrinsic to the conventional LDD structure with n+-togate offset.…”

Section: Introductionmentioning

confidence: 96%

A new LDD transistor with inverse-T gate structure

Huang

Yao

Martin

et al. 1987

IEEE Electron Device Lett.

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A new submicrometer inverse-T lightly doped drain (ITLDD) transistor structure for alleviating hot-electron effects is demonstrated. A thin extension of the polysilicon gate under the oxide sidewall spacer is formed, giving the gate cross section the appearance of an inverted letter T. Due to the unique self-aligned n--to-gate feature facilitated by the conducting polysilicon extension, the "spacer-induced degradation" existing in a conventional LDD transistor is eliminated in ITLDD devices. This allows the use of low n-LDD doses for optimum channel electric field reduction and minimum post-implant drive-in for future VLSI compatibility. Submicrometer ITLDD transistors with good transconductance and hot-electron reliability have been achieved. The new ITLDD transistor offers a promising device structure for future YLSI applications.

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