Mechanism and Origin of Hysteresis in Oxide Thin-Film Transistor and Its Application on 3-D Nonvolatile Memory

Low-Voltage, Full-Swing InGaZnO-Based Inverters Enabled by Solution-Processed, Ultra-Thin AlxOy

“…The subthreshold swing, SS, is found to be 82 and 87 mV/dec for TFT1 and TFT2, respectively, both of which are close to the theoretical limit of SS at 300 K [14]. A small clockwise hysteresis is found in the transfer characteristics of TFT2, which is likely due to the charge trapping effects at the dielectric/channel interface [15] and is considered as the reason for the slightly drop of drain current, ID, in the output characteristics shown in Fig. 2(b).…”

Characterization of a 2D Electron Gas at the Interface of Atomic‐Layer Deposited Al2O3/ZnO Thin Films for a Field‐Effect Transistor

“…In general, the clockwise hysteresis loop is related to the traps at the channel interface, and the CCW hysteresis is induced by the movement of the mobile charge in the gate oxide or the dipole polarization at the interface. [ 32 ] During the a ‐AO ALD process, TMA precursor with strong reduction kinetics was pulsed to the top of ZnO such that a substantial density of V O 's was distributed at the a‐ AO/ZnO interface as indicated in the above‐mentioned XPS. It had been reported that V O 's could migrate toward the gate electrode with the application of the high electric field in the a ‐AO during the negative V G application to the gate electrode.…”

Investigating the Reasons for the Difficult Erase Operation of a Charge‐Trap Flash Memory Device with Amorphous Oxide Semiconductor Thin‐Film Channel Layers

“…Recent studies that reported the negative V th shift in the erase operation using oxide semiconductors such as ZnO and IGZO as the CTL presumed that the lateral diffusion of injected charges occurred in such CTLs. [ 13,19–22 ] However, this is not applicable to the V‐NAND type device, where the adoption of the conducting CTL is much more tricky than the insulating CTL.…”