Mechanical stress management for electrical chip-package interaction (e-CPI)

Zhao, Wei; Nakamoto, Mark; Vidhya, R.; Radojcic, Riko

doi:10.1109/ectc.2014.6897447

Cited by 4 publications

(3 citation statements)

References 6 publications

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“…Modeling and characterization of both silicon and package are also critical for establishing design rules, process developments and risk assessments. A more complete discussion of these enablements/infrastructures can be found in various papers [3]- [5]. …”

Section: Complications Of Managing E-cbimentioning

confidence: 99%

“…As a result, transistor characteristic deviates from silicon foundry models and wafer probing results, which most often catches chip designers by surprise. We call this emerging risk electrical chip-package interaction (e-CPI) [5].…”

Section: Figure 1 Structure Of a Fccsp Packagementioning

confidence: 99%

“…Naturally, the thinner the silicon die is, the more vulnerable it is to e-CPI risk. Common e-CPI stress sources include flip chip bump, die edges/corners and stacked dies [4], [5]. Those e-CPI stress sources can affect circuits near them by introducing parametric mismatches in analog circuits, and by adding extra overhead to process, voltage and temperature (PVT) corners in digital circuits.…”

Section: Figure 1 Structure Of a Fccsp Packagementioning

confidence: 99%

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Chip Package Interaction (CPI)

2017

Advancing Microelectronics Magazine

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Section: Complications Of Managing E-cbimentioning

confidence: 99%

Section: Figure 1 Structure Of a Fccsp Packagementioning

confidence: 99%

Section: Figure 1 Structure Of a Fccsp Packagementioning

confidence: 99%

See 1 more Smart Citation

Chip Package Interaction (CPI)

2017

Advancing Microelectronics Magazine

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Impact of 3D stacking on the TSV-induced stress and the CMOS characteristics

Dote

Tashiro

Kitada

et al. 2017

2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)

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Carrier Mobility Shift in Advanced Silicon Nodes Due to Chip-Package Interaction

Sukharev¹,

Choy

Kteyan³

et al. 2017

Journal of Electronic Packaging

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Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced three-dimensional (3D) integrated circuit (IC) technologies are outlined. The growing need for a simulation-based design verification flow capable of analyzing and detecting across-die out-of-spec stress-induced variations in metal–oxide–semiconductor field-effect transistor and fin field-effect transistor (MOSFET/FinFET) electrical characteristics is highlighted. A physics-based compact modeling methodology for multiscale simulation of all the contributing components of stress-induced variability is described. A simulation flow that provides an interface between layout formats and finite element analysis (FEA)-based package-scale tools is developed. This flow can be used to optimize the chip design floorplan for different circuits and packaging technologies and/or for the final design signoff. Finally, a calibration technique based on fitting to measured electrical characterization data is presented, along with the correlation of the electrical characteristics to direct physical strain measurements.

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Mechanical stress management for electrical chip-package interaction (e-CPI)

Cited by 4 publications

References 6 publications

Chip Package Interaction (CPI)

Chip Package Interaction (CPI)

Impact of 3D stacking on the TSV-induced stress and the CMOS characteristics

Carrier Mobility Shift in Advanced Silicon Nodes Due to Chip-Package Interaction

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