Measuring delay time in adders using circuit simulation

Hsu, Yuang-Ming; Swartzlander, Earl E.

doi:10.1109/mwscas.1994.519236

Cited by 5 publications

References 1 publication

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High-Performance Low-Power Full-Swing Full Adder Cores with Output Driving Capability

Tung

Shieh

Hung

et al. 2006

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

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By using hybrid various CMOS and pass transistor logic (PTL) design approaches, two novel low-power full-swing full adder cores with output driving capability are proposed for high-performance embedded structure. The main design objectives for these full adder cores are providing not only low power and high speed but also full-swing operation at a low supply voltage and the driving capability. The simulation results show that the proposed full adder core (design-1) is superior to other designs. It consumes 17.69% to 36.21% less power than three previous designs excluding 7.87% penalty than CMOS scheme, while it is 1.88% to 53.64% faster for sum and 11.64% to 40.67% faster for carry-out than all reference full adders. The proposed design-1 has even 19.91% to 83.81% better powerdelay product (PDP) for sum and 2.86% to 93.01% better PDP for carry-out. Experimental results confirm that both of the proposed full adder cores are valid and effective.

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