Measures to achieve 20nm IPL stencil mask distortion

Abstract

From detailed comparisons of stencil mask distortion measurements with Finite Element (FE) analyses the parameters of influence are well known. Most of them are under control of the mask manufacturer, such as the membrane stress level and the etching process. By means of FE analysis the different contributions may be classified. Some of the errors can be reduced if more stringent specifications of the SOT wafer are fulfilled, some of them may be reduced after pre-calculation. Reduction of the remaining placement errors can be achieved if specific means of an Ion Projection Lithography (IPL) tool are applied. These are mainly magnification and anamorphic corrections removing so-called global distortions. The remaining local distortions can be further reduced by applying the concept of thermal mask adjustment (THEMA). I Stencil Mask Production 501 wafers purchased from the manufacturer are the basic material for the production of IPL stencil masks [1 j. Currently 3jnn thick Si membrane layers are used, but successful tests have already been done with layers down to l.8jtm thickness. SOl wafer manufacturers essentially apply two different techniques for wafer production: (i) bonding of wafers with thermally grown Si-oxide, and (ii) Oxygen ion beam implantation into Si to form a buried oxide layer after annealing. During this annealing step the SOT layer recovers the original Si lattice of the base wafer. The final thickness of the SOl layer is produced either by partial removal of one of the bonded wafers or by epitaxial growth of Si in the other case. Depending on the technique used for SOl mask wafer blank production the mechanical situation ofthe final mask membrane is different. Detailed knowledge of the SOT wafer production is necessary for understanding the distortion behavior of the stencil mask. Although the manufacturers were cooperative there is still a lack of information to understand completely the mechanical consequences ofthe bonding process as well as ofthe reformation of the partially destroyed Si lattice. Nevertheless, most types of 501 wafers that have been used within the IPL (Ion Projection Lithography) research project so far were suitable for stencil mask production. A comparison of different SOI wafer materials used for stencil mask production has already been published [2].The following sections focus on the distortions of the patterned area of stencil masks in order to obtain specifications for SOT wafers and to develop measures for additional distortion correction in the TPL tool.In this paper the terminus "SQl wqftr" will often be used instead of "SQl mask wafer blank" for simplicity. 2 Sources of Stencil Mask Distortion All placement measurements have been carried out with the Leica LMS 1PRO tool at the Infineon Technologies Mask House in Munich. A horizontal 3-point support is applied for the LMS IPRO placement measurements. For stencil masks a specific holder has been developed [3] which protects the mask from the air flow inside the cabin and avoids membrane vibrations. The repeatabil...

Mechanical characterization of membrane like microelectronic components

“…In order to acquire information on the effect of anisotropic initial wafer prestress numerical analyses of large Silicon membranes have been performed using Finite element method [7]. To get estimation for the effect of different xand y-stress three different nominal stress components values have been assumed.…”

Large-field particle beam optics for projection and proximity printing and for maskless lithography

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