Measurements on Gallium Arsenide building blocks and implications for analog IC design

Abstract

Gallium Arsenide technology has offered the promise of very high frequency opeation but its potential has not been fully realized due to technological problems which have revealed themselves in undesirable and unpredictable device characteristics. This article presents measured DC characteristics for some current mirrors and transconductors which are believed to be important building blocks for future high-speed GaAs communication circuits. The results presented validate the building block designs within the measurement limitations and show that technology improvements are now producing devices of sufficient quality to allow a sophisticated approach to GaAs circuit designs.

CMOS compatible high-voltage compliant MESFET-based analogue IC building blocks

“…2a consists of an SOS MESFET input pair and an inverting current mirror that replaces an active load [4]. The main drawback of an SOS MESFET inverting current mirror is the lower output resistance at the output nodes compared to its CMOS conterpart.…”

“…To address this limitation, an inverting current mirror (shown in Fig. 1) formed with cross-coupled gate source nodes is used [4].…”

Analog image processing circuit with 0.25µm CMOS compatible SOS MESFETs

“…However, because a p-type MESFET was not available for this process flow, an n-type only design was used for the OTAs. To address this limitation, an inverting current mirror formed with cross coupled gate source nodes is used [8]. Due to the inherent low output resistance of the MESFET based amplifiers, the MESFET based OTA with cascoded current mirror has been chosen in the design of the unit cell in order to increase the output impedance [2].…”

Integrated microwave continuous-time active filters using fully tunable GaAs transconductors

“…Alternatively, M4, M5 and M6, M7 may each be regarded as an inverting non-linear current mirror [12]. (Measured DC performance of both types of current mirror are presented in [13]). For the architectqre in Fig 2, 1) of the circuit in Fig 2 is 4go.…”