CMOS compatible high-voltage compliant MESFET-based analogue IC building blocks

Kim, S.; Lepkowski, William; Thornton, Trevor; Bakkaloglu, Bertan

doi:10.1049/el.2009.1130

Cited by 4 publications

(4 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The MESFET-based OTA was implemented in a cascoded configuration in order to increase the output impedance [12]. MOSFETs are employed in order to implement OTAs emulating discrete resistors.…”

Section: Analog Image Recognition Arraysmentioning

confidence: 99%

Analog image recognition arrays design by using co-fabricated MOSFET and MESFETs on a 0.25 μm SOS process

Kim

Lepkowski

Thornton

et al. 2012

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

This paper presents an analog image recognition system with a novel MESFET device fabricated on a fully depleted (FD) CMOS process. An analog image recognition system with a power consumption of 2.4 mW/cell and a settling time of 6.5 ls was designed, fabricated and characterized. A CNN is employed to realize a core cell of the proposed image recognition system. While a CNN benefits from its regular structure, it faces challenges due to its power consumption, speed, and size in their CMOS implementations. SOS MESFETs can deal with the challenges associated with CMOS-based CNNs. Advantages of SOS MESFETs associated with nonlinear signal processing include lower power consumption and higher operating speeds compared to similar geometry MOSFETs carrying the same current. SOS MES-FET-based analog image recognition systems were fabricated and the transient response is characterized in both simulation using a TOM3 SPICE model extracted from SOS MESFETs and in experiment using image testing lab equipment. Settling times of 3.5 and 6.5 ls for one-by-four and one-by-eight arrays, respectively, were achieved with line recognition template. The corresponding power consumption for the two arrays was 9.6 and 19.2 mW, respectively.

show abstract

Section: Analog Image Recognition Arraysmentioning

confidence: 99%

Analog image recognition arrays design by using co-fabricated MOSFET and MESFETs on a 0.25 μm SOS process

Kim

Lepkowski

Thornton

et al. 2012

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

show abstract

“…To address this limitation, an inverting current mirror formed with cross coupled gate source nodes is used [8]. Due to the inherent low output resistance of the MESFET based amplifiers, the MESFET based OTA with cascoded current mirror has been chosen in the design of the unit cell in order to increase the output impedance [2].…”

Section: Analog Neural Networkmentioning

confidence: 99%

Analog image processing circuit with 0.25µm CMOS compatible SOS MESFETs

Kim

Lepkowski

Thornton

et al. 2010

2010 IEEE International SOI Conference (SOI)

Self Cite

View full text Add to dashboard Cite

Image processing with Analog Neural Networks, performing horizontal line detection is demonstrated in a single poly, 3-layer metal digital CMOS technology utilizing SOS MESFET devices. Transient characteristics are measured by applying several combinations of grayscale input images. The measured transient response of the ANN array shows good agreement with simulations based on a TOM3 model extracted from the SOS MESFET. A worst case settling time of 4μs is achieved with the line detector.

show abstract

“…Since then the MESFETs have been demonstrated at four different foundries, using technology nodes from 350nm to 150nm. The MESFETs can be seamlessly integrated with either partially-depleted [2][3][4] or fully-depleted [5,6] SOI (silicon-on-insulator) technologies with characteristics that augment those of the ULSI CMOS. Very recently a 45nm PD-SOI CMOS foundry has been used to fabricate SOI MESFETs with the highest f max and current drive reported to date.…”

Section: Introductionmentioning

confidence: 99%

“…In [7] an SOI MESFET was configured as a source follower pass transistor controlled by a CMOS error amplifier to provide stable voltage regulation under all load conditions. Integrated CMOS-MESFET analog building blocks have been described in [6]. For RF applications a cascode architecture with a MOSFET as the common-source device and a MESFET as the common-gate is attractive for high efficiency power amplifiers that can tolerate wider voltage excursions than the baseline CMOS devices alone.…”

Section: Introductionmentioning

confidence: 99%

SILICON-ON-INSULATOR MESFETs AT THE 45nm NODE

LEPKOWSKI¹,

WILK²,

GHAJAR³

et al. 2013

Selected Topics in Electronics and Systems

View full text Add to dashboard Cite

Metal-semiconductor field-effect-transistors (MESFETs) have been fabricated using a commercially available 45nm silicon-on-insulator (SOI) CMOS foundry with no changes to the process flow. Depending upon the layout dimensions, these n-channel, depletion mode devices can be designed for high current drive (ID SAT ≥ 100mA/mm), high operating frequency ( fmax >35 GHz) or enhanced breakdown voltage (VBD >25V). The design flexibility provided by the SOI MESFETs, coupled with the high performance of ULSI CMOS at the 45nm node will enable a variety of analog, RF and mixed signal applications.

show abstract

CMOS compatible high-voltage compliant MESFET-based analogue IC building blocks

Cited by 4 publications

References 4 publications

Analog image recognition arrays design by using co-fabricated MOSFET and MESFETs on a 0.25 μm SOS process

Analog image recognition arrays design by using co-fabricated MOSFET and MESFETs on a 0.25 μm SOS process

Analog image processing circuit with 0.25µm CMOS compatible SOS MESFETs

SILICON-ON-INSULATOR MESFETs AT THE 45nm NODE

Contact Info

Product

Resources

About

CMOS compatible high-voltage compliant MESFET-based analogue IC building blocks

Cited by 4 publications

References 4 publications

Analog image recognition arrays design by using co-fabricated MOSFET and MESFETs on a 0.25 μm SOS process

Analog image recognition arrays design by using co-fabricated MOSFET and MESFETs on a 0.25 μm SOS process

Analog image processing circuit with 0.25&#x00B5;m CMOS compatible SOS MESFETs

SILICON-ON-INSULATOR MESFETs AT THE 45nm NODE

Contact Info

Product

Resources

About

Analog image processing circuit with 0.25µm CMOS compatible SOS MESFETs