Analog image recognition arrays design by using co-fabricated MOSFET and MESFETs on a 0.25 μm SOS process

Abstract

This paper presents an analog image recognition system with a novel MESFET device fabricated on a fully depleted (FD) CMOS process. An analog image recognition system with a power consumption of 2.4 mW/cell and a settling time of 6.5 ls was designed, fabricated and characterized. A CNN is employed to realize a core cell of the proposed image recognition system. While a CNN benefits from its regular structure, it faces challenges due to its power consumption, speed, and size in their CMOS implementations. SOS MESFETs can deal with the challenges associated with CMOS-based CNNs. Advantages of SOS MESFETs associated with nonlinear signal processing include lower power consumption and higher operating speeds compared to similar geometry MOSFETs carrying the same current. SOS MES-FET-based analog image recognition systems were fabricated and the transient response is characterized in both simulation using a TOM3 SPICE model extracted from SOS MESFETs and in experiment using image testing lab equipment. Settling times of 3.5 and 6.5 ls for one-by-four and one-by-eight arrays, respectively, were achieved with line recognition template. The corresponding power consumption for the two arrays was 9.6 and 19.2 mW, respectively.