McPAT

Li, Sheng; Ahn, Jung Ho; Strong, Richard; Brockman, Jay B.; Tullsen, Dean M.; Jouppi, Norman P.

doi:10.1145/1669112.1669172

Cited by 1,884 publications

(39 citation statements)

References 36 publications

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“…We estimate area overhead of the Swarm Core microarchitecture by using CMOS circuit area models in McPAT [10] and CACTI [11]. We assume affinity value is a 32-bit fixed point value and all registers in Run Queue Buffer except for Core Affinity is 64-bit.…”

Section: Discussionmentioning

confidence: 99%

Swarm Processor System: hardware process scheduler based energy efficient multi-core system

Jeong

Kim

Lee

et al. 2014

IEICE Electron. Express

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Single-ISA heterogeneous multi-core processors can provide energy efficient performance by properly assigning workloads on two types of cores in a processor: high performance large cores and low power small cores. However, traditional process scheduling mechanism is hard to support an proper workload distribution due to an overhead of fine-grained state monitoring and scheduling. To overcome this problem, we propose Swarm Processor System which supports hardware implemented workload scheduling mechanism. In the proposed system, each core chooses a proper workload by using special hardware modules in the core instead of the scheduler of operating systems. We compare Swarm Processor System against the traditional mechanisms, and found that the proposed method shows the closest energy efficiency to the oracle case with providing stable performance.

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Section: Discussionmentioning

confidence: 99%

Swarm Processor System: hardware process scheduler based energy efficient multi-core system

Jeong

Kim

Lee

et al. 2014

IEICE Electron. Express

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“…Because the memory footprints of the evaluated workloads (193 MB-1.6 GB) are smaller than DRAM cache size (16 GB), we scaled down DRAM cache size to a quarter of workload footprint for each simulation by reducing the number of rows per bank. The latency/energy parameters of processor (14 nm technology), DRAM, and PCM are extracted from a modified McPAT [19], Micron datasheet, and previous studies [10,17,18], respectively. We adopted PAR-BS [16] as a memory request scheduling policy and adaptive open/close policy (which is also adopted at Intel Xeon™ series) as a DRAM/PCM page management policy.…”

Section: Experimental Methodologymentioning

confidence: 99%

Selective DRAM cache bypassing for improving bandwidth on DRAM/NVM hybrid main memory systems

Sung

Park

et al. 2017

IEICE Electron. Express

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Satisfying a demand for higher memory capacity is a major problem for computing systems. Conventional solutions are reaching those limits; instead, DRAM/NVM hybrid main memory systems which consist of emerging Non-Volatile Memory for large capacity and DRAM last-level cache for high access speed were proposed for further improvement. However, in these systems, the two device types share limited memory channels/ ranks and NVM channels/ranks are often less utilized than DRAM ones. This paper proposes an OBYST (On hit BYpass to STeal bandwidth) technique to improve memory bandwidth by selectively sending read requests that hit on DRAM cache to NVM instead of busy DRAM. We also propose an inter-device request scheduling policy optimized to OBYST. With negligible area overhead, OBYST improves bandwidth, IPC, and EDP by up to 22%, 21%, and 26% over the baseline without bandwidth optimizations, respectively.

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“…On the other hand, we use CACTI to estimate the power and area of the three caches included in the accelerator. We employ the version of CACTI provided in McPAT [26], a.k.a. enhanced CACTI [27] which includes models for 28 nm.…”

Section: Evaluation Methodologymentioning

confidence: 99%

An ultra low-power hardware accelerator for automatic speech recognition

Yazdani¹,

Segura²,

Arnau³

et al. 2016

2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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Abstract-Automatic Speech Recognition (ASR) is becoming increasingly ubiquitous, especially in the mobile segment. Fast and accurate ASR comes at a high energy cost which is not affordable for the tiny power budget of mobile devices. Hardware acceleration can reduce power consumption of ASR systems, while delivering high-performance.In this paper, we present an accelerator for large-vocabulary, speaker-independent, continuous speech recognition. It focuses on the Viterbi search algorithm, that represents the main bottleneck in an ASR system. The proposed design includes innovative techniques to improve the memory subsystem, since memory is identified as the main bottleneck for performance and power in the design of these accelerators. We propose a prefetching scheme tailored to the needs of an ASR system that hides main memory latency for a large fraction of the memory accesses with a negligible impact on area. In addition, we introduce a novel bandwidth saving technique that removes 20% of the off-chip memory accesses issued during the Viterbi search.The proposed design outperforms software implementations running on the CPU by orders of magnitude and achieves 1.7x speedup over a highly optimized CUDA implementation running on a high-end Geforce GTX 980 GPU, while reducing by two orders of magnitude (287x) the energy required to convert the speech into text.

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McPAT

Cited by 1,884 publications

References 36 publications

Swarm Processor System: hardware process scheduler based energy efficient multi-core system

Swarm Processor System: hardware process scheduler based energy efficient multi-core system

Selective DRAM cache bypassing for improving bandwidth on DRAM/NVM hybrid main memory systems

An ultra low-power hardware accelerator for automatic speech recognition

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