MCM-D/C packaging solution for IBM latest S/390 servers

Perfecto, Eric; Shields, R.R.; Malhotra, A. K.; Jeanneret, M.P.; McHerron, Dale; Katopis, G.A.

doi:10.1109/6040.861568

Cited by 6 publications

(1 citation statement)

References 10 publications

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“…Figure 1(b) shows the face-to-face approach of joining the front sides of two wafers. IBM originally used this method [12] to create MCMs with an interconnect pitch of less than 20 lm with reduced process complexity compared to the face-to-back scheme. A key potential advantage of face-to-face assembly is the ability to decouple the number of TSVs from the total number of interconnections between the layers.…”

Section: Basic 3d Integration Approachesmentioning

confidence: 99%

Wafer-level 3D integration technology

et al. 2008

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An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed. IntroductionThe last few decades have seen an astonishing increase in the functionality of computational systems. This capability has been driven by the scaling of semiconductor devices, which has enabled the number of transistors on a single chip to grow at a geometric rate, following Moore's Law [1]. In particular, the scaling of silicon metal-oxide semiconductor field-effect transistors (MOSFETs) [2] drives the effort to continue this trend into the future.However, several serious roadblocks exist. The first is the difficulty and expense of continued lithographic scaling, which could make it economically impractical to scale devices beyond a certain pitch. The second is that even if lithographic scaling can continue, the power dissipated by the transistors will bring clock frequency scaling to a halt. In fact, it could be argued that clock frequency scaling has already stopped, and microprocessor designs have increasingly relied on new architectures to improve performance. These factors suggest that in the near future, it will no longer be possible to improve system performance through scaling alone, and that additional methods to achieve the desired enhancement will be needed. Three-dimensional (3D) integration technology offers the promise of being a new way of increasing system performance, even in the absence of scaling. This promise is due to a number of characteristic features of 3D integration, including decreased total wiring length (and thus reduced interconnect delay times), a dramatically increased number of interconnects between chips, and the ability to allow dissimilar materials, process technologies, and functions to be integrated. Motivation for 3D integration

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Section: Basic 3d Integration Approachesmentioning

confidence: 99%

Wafer-level 3D integration technology

et al. 2008

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RF/Wireless Packaging

Pinel

Tentzeris

Staicnlescu

et al. 2005

Encyclopedia of RF and Microwave Engineering

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The electronics packaging industry has proliferated to a point where its technology is at least equally—the semiconductor technology it is designed to serve. The increase in silicon complexity and integration has imposed demanding requirements on packaging technology for higher I/O counts, finer lead pitch, enhanced heat dissipation, and high‐speed, reliable interconnects. At the same time, the industry is also driving toward reduced printed‐circuit‐board area and complexity. From the traditional role of a protective mechanical enclosure, the modern package has been transformed into a sophisticated thermal and electrical management platform. Recent advances in high‐frequency packaging indicate a migration from wirebond (where the chip or die is interconnected to the package only on the periphery of the die) to flip‐chip (where the die is interconnected to the package using the entire die area); and from ceramic to organic packages, with cartridge and multichip technologies emerging as key form factors. The RF front‐end module is the core of the complex systems, and its integration poses a great challenge. Considering the characteristics of the RF modules, such as high performance up to 100 GHz; a large number of high‐performance discrete passive components, design flexibility, reconfigurable architecture, low power consumption, compactness, customized product, short time to market, and low cost, the system‐on package (SoP ) approach has emerged as the most effective means to provide a realistic integration solution as opposed to the system‐on‐chip (SoC ) solution. The strength of SoP is based on multilayer technololgy using low‐cost and high‐performance materials.

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3D Process Technology Considerations

Young

Koester

2009

Integrated Circuits and Systems

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MCM-D/C packaging solution for IBM latest S/390 servers

Cited by 6 publications

References 10 publications

Wafer-level 3D integration technology

Wafer-level 3D integration technology

RF/Wireless Packaging

3D Process Technology Considerations

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