Maximizing Parallelism without Exploding Deadlines in a Mixed Criticality Embedded System

Abstract

Complex embedded systems today commonly involve a mix of real-time and besteffort applications. The recent emergence of small low-cost commodity UMA multicore processors raises the possibility of running both kinds of applications on a single machine, with virtualization ensuring that the best-effort applications cannot steal CPU cycles from the real-time applications. Nevertheless, memory contention can introduce other sources of delay, that can lead to missed deadlines. In this research report, we present a combined offline/online memory bandwidth monitoring approach. Our approach estimates and limits the impact of the memory contention incurred by the best-effort applications on the execution time of the real-time application. We show that our approach is compatible with the hardware counters provided by current small commodity multicore processors. Using our approach, the system designer can limit the overhead on the real-time application to under 5% of its expected execution time, while still enabling progress of the best-effort applications.

Improving Prediction Accuracy of Memory Interferences for Multicore Platforms

“…We characterize the intensity of memory behavior with the bandwidth to shared memory, as it is fairly common, notably in regulation systems such as MemGuard [2] or the approach proposed by Blin et al [3]. We use the counters provided by the Performance Monitoring Unit (PMU) of the MMDC to measure it.…”

“…An alternative approach is proposed by Blin et al [3] to keep under a specified threshold the slowdown caused by best efforts application to a real-time one. In this approach, an interference model of the hardware platform is built using measures.…”

“…Such estimation can be used in practice to quickly assess the suitability of a platform for a particular workload and ease the hardware provisioning of real-time systems. Our work is based on the observation that existing approaches to determine interference overhead rely only on bandwidth measurement which leads to conservative pessimistic values [2] [3]. We make three contributions.…”

Modelling Multicore Contention on the AURIX™ TC27x

“…Automotive industry is increasingly adopting multicores as the reference computing solution for ECUs [1][2][3]. Yet, several academic and industrial studies show that multicores have disruptive effects on Validation and Verification (V&V) practice, shaped on singlecore architectures: timing analysis techniques have to be carefully adapted to factor in multicore contention in WCET estimates [5,14].…”

Understanding the Memory Consumption of the MiBench Embedded Benchmark

“…Therefore, it has been observed that the memory usage of applications running on one core may impact the execution time of applications running on the other cores [19,21]. In recent work [13], we have shown that sharing these resources implies that the operations initiated on a best-effort core can affect the duration of real-time tasks running on other cores. In that work, we have developed an approach to address the memory induced slowdown that uses run-time monitoring to detect when the interference risks causing the real-time task to exceed its deadline beyond a threshold that is considered to be tolerable.…”