Modelling Multicore Contention on the AURIX™ TC27x

Abstract

Multicores are becoming ubiquitous in automotive. Yet, the expected benefits on integration are challenged by multicore contention concerns on timing V&V. Worst-case execution time (WCET) estimates are required as early as possible in the software development, to enable prompt detection of timing misbehavior. Factoring in multicore contention necessarily builds on conservative assumptions on interference, independent of co-runners load on shared hardware. We propose a contention model for automotive multicores that balances time-composability with tightness by exploiting available information on contenders. We tailor the model to the AURIX TC27x and provide tight WCET estimates using information from performance monitors and software configurations.

Much

“…Several works build on HEMs for multicore timing analysis, for bound estimation and online monitoring [23], [34], [35], [36]. On the industrial side, HEMs have also been exploited to produce timing evidence needed for certification on multicores [27], [37].…”

HRM: Merging Hardware Event Monitors for Improved Timing Analysis of Complex MPSoCs

“…Paulisch et al [21] create an analysis and runtime monitoring solution for limiting task contention in multicores by tracking and controlling HEM. In the same vein, Diaz et al [38] build on HEM to produce an ILP-based contention model for an AURIX automotive microcontroller. Likewise, Santinelli et al [39], build on the HEM of a multicore system to derive probabilistic WCET estimates.…”

On the reliability of hardware event monitors in MPSoCs for critical domains

“…PMUs are an effective means to derive additional (and complementary) information on the contention delay tasks can suffer [11], [29], [12]. While PMUs may vary depending on the different architecture and family of processors and platforms, they generally offer the capability to track a large number of events, typically in the extent of few hundreds or even thousands, related to multiple aspects of execution: from cache-hierarchy statistics to accesses over the interconnects, as well as instruction counts for the different instruction types.…”

“…The fine-grained information that can be obtained from hardware event monitors can be used to improve the understanding of the timing behaviour of an application [11], [12], to enforce usage thresholds for shared components [29], and to define a more accurate timing model of contention-prone hardware resources [12]. Ultimately, these aspects concur with the sought-after properties of freedom from interference in ISO26262 (and interference channels identification in CAST-32A) to guarantee timing faults cannot propagate across software elements with different criticality levels.…”