MAX-PolyMem: High-Bandwidth Polymorphic Parallel Memories for DFEs

Ciobanu, Catalin Bogdan; Stramondo, Giulio; Laat, Cees de; Vărbănescu, Ana Lucia

doi:10.1109/ipdpsw.2018.00025

Cited by 5 publications

(5 citation statements)

References 18 publications

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“…In summary, compared to previous work on enabling easy-to-use memory hierarchies and/or caching mechanisms for FPGAs, PolyMem proposes a PRFbased design that supports polymorphic parallel accesses through a single, multiview, application-specific software cache. The previous HLS implementation [3] has demonstrated good performance, but was specifically designed to be used on Maxeler-based systems. Our current HLS-PolyMem is the most generic implementation to date, it preserves the advantages of the previous incarnations of the system in terms of performance and flexibility, and adds the ease-of-use of an HLS library that can be easily integrated in the design flow of modern tools like Vivado HLx and Vivado SDx.…”

Section: Related Workmentioning

confidence: 99%

“…To address the challenges related to the design and practical use of parallel memory systems for FPGA-based applications, PolyMem, a Polymorphic Parallel Memory, was proposed [3]. PolyMem is envisioned as a high-bandwidth, twodimensional (2D) memory used to cache performance-critical data on the FPGA chip, making use of the distributed memory banks (the BRAMs).…”

Section: Introductionmentioning

confidence: 99%

“…The first hardware implementation of the Polymorphic Register File was designed in System Verilog [5]. MAX-PolyMem is the first prototype of PolyMem written entirely in MaxJ, and targeted at Maxeler Data Flow Engines (DFEs) [3,6]. Our new HLS PolyMem is an alternative HLL solution, proven to be easily integrated with the Xilinx toolchains.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS

Stornaiuolo

Rabozzi

Santambrogio

et al. 2019

VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms

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With the increased interest in energy efficiency, a lot of application domains experiment with Field Programmable Gate Arrays (FPGAs), which promise customized hardware accelerators with highperformance and low power consumption. These experiments possible due to the development of High-Level Languages (HLLs) for FPGAs, which permit non-experts in hardware design languages (HDLs) to program reconfigurable hardware for general purpose computing. However, some of the expert knowledge remains difficult to integrate in HLLs, eventually leading to performance loss for HLL-based applications. One example of such a missing feature is the efficient exploitation of the local memories on FPGAs. A solution to address this challenge is PolyMem, an easy-to-use polymorphic parallel memory that uses BRAMs. In this work, we present HLS-PolyMem, the first complete implementation and in-depth evaluation of PolyMem optimized for the Xilinx Design Suite. Our evaluation demonstrates that HLS-PolyMem is a viable alternative to HLS memory partitioning, the current approach for memory parallelism in Vivado HLS. Specifically, we show that Poly-Mem offers the same performance as HLS partitioning for simple access patterns, and outperforms partitioning as much as 13x when combining multiple access patterns for the same data structure. We further demonstrate the use of PolyMem for two different case studies, highlighting the superior capabilities of HLS-PolyMem in terms of performance, resource utilization, flexibility, and usability. Based on all the evidence provided in this work, we conclude that HLS-PolyMem enables the efficient use of BRAMs as parallel memories, without compromising the HLS level or the achievable performance.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS

Stornaiuolo

Rabozzi

Santambrogio

et al. 2019

VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms

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show abstract

“…To address the challenges related to the design and practical use of parallel memory systems, we propose PolyMem [26], a Polymorphic Parallel Memory. We envision PolyMem as a high-bandwidth, two-dimensional (2D) memory which is used to cache performancecritical data right on the FPGA chip, making use of the existing distributed memory banks (the BRAMs).…”

Section: The Extra Parallel Memory Systemmentioning

confidence: 99%

“…The Addressing Function A computes, for each accessed element, the intra-memory bank address. In [26], a multi-dimensional Design Space Exploration (DSE) approach was used, where the capacity, number of lanes, and number of read ports for each PolyMem scheme were empirically evaluated. Our results show that (1) MAX-PolyMem can utilize the entire capacity of on-chip BRAMs, allowing the instantiation of a 4MB parallel memory on the Maxeler Vectis DFE; (2) the MaxJ design delivers up to 22GB/s write bandwidth and up to 32GB/s aggregated read bandwidth using up to 4 read ports, at a clock frequency of up to 202MHz, and (3) we are able to utilize all the available BRAMs with reasonable logic utilization.…”

Section: Max-polymem: Polymem For Dfesmentioning

confidence: 99%

Extra

Ciobanu

Stramondo

Vărbănescu

et al. 2018

Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

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Reconfigurable hardware is becoming increasingly mainstream, evolving to a valid alternative to Graphics Processing Units-based hardware accelerators. However, several major challenges remain for migrating existing software to heterogeneous reconfigurable architectures. The EXTRA project aims to develop an integrated environment for developing and programming reconfigurable architectures. The EXTRA platform enables the joint optimization of architecture, tools, and reconfiguration technology, and targets the future High Performance Computing hardware nodes. In this paper, we present four innovative EXTRA technologies: (1) a hardwaresoftware co-design framework; (2) a parallel memory system; (3) a decoupled access execute framework for reconfigurable technology; and (4) transparent access and virtualization of reconfigurable hardware accelerators. Moreover, we describe how the EXTRA technologies targeting the Amazon F1 cloud compute instances can be used in medical applications such as the retinal image segmentation. CCS CONCEPTS • Computer systems organization → Reconfigurable computing; Data flow architectures; • Hardware → Hardware accelerators; Hardware-software codesign;

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Designing and building application‐centric parallel memories

Stramondo

Ciobanu

Laat

et al. 2019

Concurrency and Computation

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SummaryMemory bandwidth is a critical performance factor for many applications and architectures. Intuitively, a parallel memory could be a good solution for any bandwidth‐limited application, yet building application‐centric custom parallel memories remains a challenge. In this work, we present a comprehensive approach to tackle this challenge and demonstrate how to systematically design and implement application‐centric parallel memories. Specifically, our approach (1) analyzes the application memory access traces to extract parallel accesses, (2) configures our parallel memory for maximum performance, and (3) builds the actual application‐centric memory system. We further provide a simple performance prediction model for the constructed memory system. We evaluate our approach with two sets of experiments. First, we demonstrate how our parallel memories provide performance benefits for a broad range of memory access patterns. Second, we prove the feasibility of our approach and validate our performance model by implementing and benchmarking the designed parallel memories using FPGA hardware and a sparse version of the STREAM benchmark.

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MAX-PolyMem: High-Bandwidth Polymorphic Parallel Memories for DFEs

Cited by 5 publications

References 18 publications

Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS

Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS

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Designing and building application‐centric parallel memories

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