Master-Slave Control Structure for Massively Parallel System on Chip

Krichene, Hana; Baklouti, Mouna; Abid, Mohamed; Marque, Philippe; Dekeyser, Jean-Luc

doi:10.1109/dsd.2013.103

Cited by 5 publications

(3 citation statements)

References 18 publications

(14 reference statements)

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“…1 shows the overview of the SCAC architecture. The SCAC architecture is characterized by hierarchical control structure distributed on two levels [8], in order to separate the control functions. The SCAC execution model is based on Asynchronous Computation to allow autonomous processing, and Synchronous Communication to ensure simple data transfer without compromising the computation.…”

Section: Scac Architecturementioning

confidence: 99%

SCAC-Net: Reconfigurable Interconnection Network in SCAC Massively Parallel SoC

Krichene

Baklouti

Marque

et al. 2016

2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)

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Parallel communication plays a critical role in massively parallel systems, especially in distributed memory systems executing parallel programs on shared data. Therefore, integrating an interconnection network in these systems becomes essential to ensure data inter-nodes exchange. Choose the most effective communication structure must meet certain criteria: speed, size and power consumption. Indeed, the communication phase should be as fast as possible to avoid compromising parallel computing, using small and low power consumption modules to facilitate the interconnection network extensibility in a scalable system. To meet these criteria and based on a module reuse methodology, we chose to integrate a reconfigurable SCAC-Net interconnection network to communicate data in SCAC Massively parallel SoC. This paper presents the detailed hardware implementation and discusses the performance evaluation of the proposed reconfigurable SCAC-Net network.

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Section: Scac Architecturementioning

confidence: 99%

SCAC-Net: Reconfigurable Interconnection Network in SCAC Massively Parallel SoC

Krichene

Baklouti

Marque

et al. 2016

2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)

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“…Distributed control systems for the MPSoCs are extensively studied in [13]- [16]. A distributed flow control strategy is designed for RF-powered wireless NoC [17].…”

Section: Introductionmentioning

confidence: 99%

Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip

Liu

Zhang

Wang

et al. 2016

IEEE Trans. VLSI Syst.

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As transistor density continues to increase with the advent of nanotechnology, reliability issues raised by more frequently appeared soft errors are becoming even more critical to the next-generation multiprocessor systems. In this paper, we present a systematic approach to address the soft-error problem in multiprocessor system-on-chip with the consideration of system performance optimization. To guarantee the system correctness, a hardware-software collaborated approach is proposed to protect the processors from soft errors. Tiny hardware sensors are embedded in the processor cores to detect the soft errors, and the software-based rollback scheduling mechanisms are applied for error recovery. The protection costs on hardware duplication and software redundancy are effectively reduced. To optimize the system performance, a distributed control system is built on top of the on-chip communication network and collaboratively manages the entire chip for application execution. With the cluster-based task migration techniques, an efficient runtime task remapping and rescheduling algorithm is proposed to further mitigate the overheads induced by soft-error protection and to minimize the total performance degradation. The distributed control strategy makes the system more adaptable and flexible to the development of the next-generation hardware and software with larger scales. Extensive performance evaluations using SystemC-based cycleaccurate simulations on a set of real-world applications show that our approach has on average 49% performance improvement and 79.6% energy consumption reduction compared with the related state-of-the-art techniques, and hardware synthesis results show that our approach only introduces 2.9% chip area overheads.

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“…According to this model, there are 6 basic elements and traditional Master/Slave code organization logic. The Master/Slave code organization logic is a variant of SPMD (Single Program Multiple Data) models which are successfully applied in parallel algorithms developing [4,5,6,7,8,9,10,11,12,13,14,15,16]. The operations are located in their exact positions depends on parallel execution.…”

Section: Introductionmentioning

confidence: 99%

One Approach for Parallel Algorithms Representation

Bosakova-Ardenska¹

2017

Balkan Journal of Electrical and Computer Engineering

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Abstract-This paper presents one approach for parallel algorithms representation. The proposed model is practice oriented and its name is AMPA (Agenda Model for Parallel Algorithms) due to basic blocks organization like a schedule. The model uses classical Master/Slave paradigm. One parallel merge sorting algorithm based on quick sort is presented with the discussed AMPA model and also three known representation approaches (description with natural language, pseudo code and PRAM). A survey of professional opinion about AMPA and other approaches is conducted. The results show that most of the interviewed people choose AMPA as the best way to understand the algorithm.

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Master-Slave Control Structure for Massively Parallel System on Chip

Cited by 5 publications

References 18 publications

SCAC-Net: Reconfigurable Interconnection Network in SCAC Massively Parallel SoC

SCAC-Net: Reconfigurable Interconnection Network in SCAC Massively Parallel SoC

Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip

One Approach for Parallel Algorithms Representation

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