Massive statistical process variations: A grand challenge for testing nanoelectronic circuits

Becker, Bernd; Hellebrand, Sybille; Polian, Ilia; Straube, Bernd; Vermeiren, Wolfgang; Wunderlich, Hans-Joachim

doi:10.1109/dsnw.2010.5542612

Cited by 11 publications

(4 citation statements)

References 28 publications

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“…Probabilistic fault modeling aims to quantify the quality of the test and final product w.r.t. the parameter space in spite of high uncertainty of variations [6].…”

Section: Resilience Articulation Point (Rap) Modelmentioning

confidence: 99%

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience

Herkersdorf

Aliee

Engel

et al. 2014

Microelectronics Reliability

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The Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System on Chip. RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flip(s). When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro-interfaces or software variables. Thus, design concerns at higher abstraction layers can be investigated without the necessity to further consider the full details of lower levels of design. This paper introduces the ideas of RAP based on examples of radiation induced soft errors in SRAM cells, voltage variations and sequential CMOS logic. It shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture-level resilience methods. AbstractThe Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System on Chip. RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flip(s). When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro interfaces or software variables. Thus, design concerns at higher abstraction layers can be investigated without the necessity to further consider the full details of lower levels of design. This paper introduces the ideas of RAP based on examples of radiation induced soft errors in SRAM cells, voltage variations and sequential CMOS logic. It shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture-level resilience methods.

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“…Probabilistic fault modeling aims to quantify the quality of the test and final product w.r.t. the parameter space in spite of high uncertainty of variations [6].…”

Section: Resilience Articulation Point (Rap) Modelmentioning

confidence: 99%

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience

Herkersdorf

Aliee

Engel

et al. 2014

Microelectronics Reliability

View full text Add to dashboard Cite

show abstract

“…Probabilistic fault modeling aims at quantifying the quality of the test and final product w.r.t. the parameter space in spite of high uncertainty of variations [26].…”

Section: Resilience Articulation Point (Rap)mentioning

confidence: 99%

Connecting different worlds - Technology abstraction for reliability-aware design and Test

Schlichtmann¹,

Veit²,

Abraham

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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The rapid shrinking of device geometries in the nanometer regime requires new technology-aware design methodologies. These must be able to evaluate the resilience of the circuit throughout all System on Chip (SoC) abstraction levels. To successfully guide design decisions at the system level, reliability models, which abstract technology information, are required to identify those parts of the system where additional protection in the form of hardware or software countermeasures is most effective. Interfaces such as the presented Resilience Articulation Point (RAP) or the Reliability Interchange Information Format (RIIF) are required to enable EDA-assisted analysis and propagation of reliability information. The models are discussed from different perspectives, such as design and test.

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“…Process variations and high defect densities in recent technology nodes have emerged as new challenges for the timing analysis and the delay test of digital integrated circuits [1]- [3]. The uncertainty in the delays of all circuit components severely degrades the quality and reliability of all delay tests, leading to many test escapes [4].…”

Section: Introductionmentioning

confidence: 99%

Incremental computation of delay fault detection probability for variation-aware test generation

Wagner

Wunderlich

2014

2014 19th IEEE European Test Symposium (ETS)

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Large process variations in recent technology nodes present a major challenge for the timing analysis of digital integrated circuits. The optimization decisions of a statistical delay test generation method must therefore rely on the probability of detecting a target delay fault with the currently chosen test vector pairs. However, the huge number of probability evaluations in practical applications creates a large computational overhead. To address this issue, this paper presents the first incremental delay fault detection probability computation algorithm in the literature, which is suitable for the inner loop of automatic test pattern generation methods. Compared to Monte Carlo simulations of NXP benchmark circuits, the new method consistently shows a very large speedup and only a small approximation error. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE. Abstract-Large process variations in recent technology nodes present a major challenge for the timing analysis of digital integrated circuits. The optimization decisions of a statistical delay test generation method must therefore rely on the probability of detecting a target delay fault with the currently chosen test vector pairs. However, the huge number of probability evaluations in practical applications creates a large computational overhead.To address this issue, this paper presents the first incremental delay fault detection probability computation algorithm in the literature, which is suitable for the inner loop of automatic test pattern generation methods. Compared to Monte Carlo simulations of NXP benchmark circuits, the new method consistently shows a very large speedup and only a small approximation error.

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Massive statistical process variations: A grand challenge for testing nanoelectronic circuits

Cited by 11 publications

References 28 publications

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience

Connecting different worlds - Technology abstraction for reliability-aware design and Test

Incremental computation of delay fault detection probability for variation-aware test generation

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