MARVLE: a VLSI chip for variable length encoding and decoding

Mukherjee, Amar; Flieder, J.; Ranganathan, N.

doi:10.1109/iccd.1992.276242

Cited by 3 publications

(7 citation statements)

References 3 publications

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“…SCMOS standard cell requires much smaller area than a CMOSN cell. Also, the design in [2] employs customized RAM cells.…”

Section: B Memory Map For Decodingmentioning

confidence: 99%

“…In addition, there is no known worst case bound on the memory needed for storing the reversed tree [15], [16]. Thus, the design in [2] may require more memory than the available memory of size 512 x 12 bits in the worst case, which may lead to failure of encoding/decoding operations.…”

mentioning

confidence: 99%

“…Compared with the storage scheme in [7], the proposed storage scheme requires less memory if log n I 10, which occurs very frequently in practice. Compared with the design in [2], our design requires about 25% of the memory. The die size of the resulting design is evaluated using CADENCE CAD tools, and 1.2 micron standard cell approach to show the feasibility of our design.…”

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confidence: 99%

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Area efficient VLSI architectures for Huffman coding

Park

Prasanna

1993

IEEE Trans. Circuits Syst. II

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Absmt--In this paper, we present simple and area efficient VLSI architectures for HufFman coding, an industrial standard proposed by MPEG, JPEG, and others. We use a memory of size O(nlogn) bits to store a HuEman code tree, where n is the number of symbols. This storage scheme supports real-time encoding and decoding. In addition, few simple arithmetic operations are performed on the chip for encoding and decoding. Based on our scheme, we show a design for &bit symbols. The proposed design requires 256 X 9 and 64 X U-bit memory modules to process 8-bit symbols. The chip occupies a silicon a m of 3.5 X 3.5 mm' using 1.2 micron CMOSN standard library cells. Compared with the known parallel implementation in [I] which requires upto 65536 PE's, the proposed architecture leads to a single PE design. It requires significantly less area than the known single PE design in 121. Different Huffknan codes can be stored by changing the contents of the memory, without changing the design. I. INTRODUC~ONLow bit rate coding is essential for image applications such as TV transmission, video conferencing, remote sensing via satellite, computer communication, facsimile transmission, etc. Data compression techniques reduce the storage and communication channel bandwidth needed to process such signals. Most conventional compression techniques require lossless coding method at the end of the encoder to obtain additional compression. In addition, some applications require lossless coding schemes. The lossless data encoding schemes can also reduce the cost of backup and recovery in computer systems and increased security and efficient search operations on compressed index structure of files. It is also useful in the design of databases [3], document delivery systems, communication networks, and high performance supercomputers [ll. Several lossless coding schemes have been proposed for these purposes. One of these lossless coding schemes is Huffman coding (also known as optimal variable length coding) which provides optimal coding for a fixed length

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“…SCMOS standard cell requires much smaller area than a CMOSN cell. Also, the design in [2] employs customized RAM cells.…”

Section: B Memory Map For Decodingmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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Area efficient VLSI architectures for Huffman coding

Park

Prasanna

1993

IEEE Trans. Circuits Syst. II

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“…Therefore, the memory bits required by the various implementations are employed here as a comparison measurement of silicon area. Compared with previous works, which require 256 Ã 9 þ 64 Ã 18 ¼ 3456 bits of memory [4], and 512 Ã 12 ¼ 6144 bits of memory [5] to process 8 bit symbols, the proposed design requires 256 Ã 8 bits of input symbol memory and 73 Ã 10 bits of temporarily available memory, for a total of 2778 bits of memory to process 8 bit symbols. This verifies a substantial decrease in silicon area for the proposed architecture.…”

Section: Introductionmentioning

confidence: 97%

“…High rate serial data encoders are essential for many applications such as image compression, data transmission, and data communication. Therefore, the proposed technological innovation is employed in a high-rate serial data encoding application implemented in VLSI using the Verilog hardware description language (HDL), and simulated using the Modelsim electronic design automation (EDA) tool of Mentor Graphics Inc. [5]. However, the required memory is the primary component of area consumption in each architecture.…”

Section: Introductionmentioning

confidence: 99%

Efficient VLSI Huffman encoder implementation and its application in high rate serial data encoding

Wei

Zhang

2017

IEICE Electron. Express

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Abstract:In this paper, we present a new data structure element for constructing a Huffman tree, and a new algorithm is developed to improve the efficiency of Huffman coding by constructing the Huffman tree synchronously with the generation of codewords. The improved algorithm is adopted in a VLSI architecture for a Huffman encoder. The VLSI implementation is realized using the Verilog hardware description language and simulated by Modelsim. The proposed scheme achieves rapid coding speed with a gate count of 9.962 K using SMIC 0.18 micron standard library cells.

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Area efficient VLSI architectures for Huffman coding

Park

Prasanna

1993

IEEE International Conference on Acoustics Speech and Signal Processing

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MARVLE: a VLSI chip for variable length encoding and decoding

Cited by 3 publications

References 3 publications

Area efficient VLSI architectures for Huffman coding

Area efficient VLSI architectures for Huffman coding

Efficient VLSI Huffman encoder implementation and its application in high rate serial data encoding

Area efficient VLSI architectures for Huffman coding

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