Mapping Multimedia Applications Onto Configurable Hardware With Parameterized Cyclo-Static Dataflow Graphs

We develop a design methodology for mapping computer vision algorithms onto an FPGA through the use of coarse-grain reconfigurable dataflow graphs as a representation to guide the designer. We first describe a new dataflow modeling technique called homogeneous parameterized dataflow (HPDF), which effectively captures the structure of an important class of computer vision applications. This form of dynamic dataflow takes advantage of the property that in a large number of image processing applications, data production and consumption rates can vary, but are equal across dataflow graph edges for any particular application iteration. After motivating and defining the HPDF model of computation, we develop an HPDF-based design methodology that offers useful properties in terms of verifying correctness and exposing performance-enhancing transformations; we discuss and address various challenges in efficiently mapping an HPDF-based application representation into target-specific HDL code; and we present experimental results pertaining to the mapping of a gesture recognition application onto the Xilinx Virtex II FPGA.

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“…We have further refined our model for the gesture recognition algorithm using CSDF [17] as the base model for HPDF.…”

Section: Modeling With Hpdf Over Csdfmentioning

confidence: 99%

Dataflow-Based Mapping of Computer Vision Algorithms onto FPGAs

Sen¹,

Corretjer²,

Haim³

et al. 2007

EURASIP Journal on Embedded Systems

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“…Other works only mention using extensions to (C)SDF to describe image [3] and video [4] applications without a formal description of these extensions. Reference [5] integrates CSDF in a parameterized dataflow model to allow dynamic data production and consumption rates. The modeling of buffer bounds by using a feedback edge is introduced in [1] for interprocessor communication graphs (a type of homogenous synchronous dataflow graph) and in [6] to explore the tradeoff between throughput and buffer requirements.…”

Section: Introductionmentioning

confidence: 99%

Exploiting the Expressiveness of Cyclo-Static Dataflow to Model Multimedia Implementations

Denolf

Bekooij

Cockx

et al. 2007

EURASIP J. Adv. Signal Process.

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The design of increasingly complex and concurrent multimedia systems requires a description at a higher abstraction level. Using an appropriate model of computation helps to reason about the system and enables design time analysis methods. The nature of multimedia processing matches in many cases well with cyclo-static dataflow (CSDF), making it a suitable model. However, channels in an implementation often use for cost reasons a kind of shared buffer that cannot be directly described in CSDF. This paper shows how such implementation specific aspects can be expressed in CSDF without the need for extensions. Consequently, the CSDF graph remains completely analyzable and allows reasoning about its temporal behavior. The obtained relation between model and implementation enables a buffer capacity analysis on the model while assuring the throughput of the final implementation. The capabilities of the approach are demonstrated by analyzing the temporal behavior of an MPEG-4 video encoder with a CSDF graph.

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“…However, to satisfy HPDF constraints, the total number of tokens produced by an actor on a given edge 'e' in a given invocation must equal the total number of tokens consumed by the corresponding invocation of the sink actor of 'e'. A more detailed and formal description of HPDF/CSDF is given in [6]. We use HPDF/CSDF in Sect.…”

Section: Dataflow Modelingmentioning

confidence: 99%

Model-based mapping of reconfigurable image registration on FPGA platforms

Sen

Hemaraj

Plishker

et al. 2008

J Real-Time Image Proc

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Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficiency. This paper develops techniques for mapping rigid image registration applications onto configurable hardware under real-time performance constraints. Building on the framework of homogeneous parameterized dataflow, which provides an effective formal model of design and analysis of hardware and software for signal processing applications, we develop novel methods for representing and exploring the hardware design space when mapping image registration algorithms onto configurable hardware. Our techniques result in an efficient framework for trading off performance and configurable hardware resource usage based on the constraints of a given application. Based on trends that we have observed when applying these techniques, we also present a novel architecture that enables dynamically-reconfigurable image registration. This proposed architecture has the ability to tune its parallel processing structure adaptively based on relevant characteristics of the input images.

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Mapping Multimedia Applications Onto Configurable Hardware With Parameterized Cyclo-Static Dataflow Graphs

Cited by 8 publications

References 12 publications

Dataflow-Based Mapping of Computer Vision Algorithms onto FPGAs

Dataflow-Based Mapping of Computer Vision Algorithms onto FPGAs

Exploiting the Expressiveness of Cyclo-Static Dataflow to Model Multimedia Implementations

Model-based mapping of reconfigurable image registration on FPGA platforms

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