Mapping an H.264/AVC decoder onto the ADRES reconfigurable architecture

Mei, Bingfeng; Veredas, F.-J.; Masschelein, Bart

doi:10.1109/fpl.2005.1515799

Cited by 20 publications

(3 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For example, Celator [58] is a reconfigurable coprocessor that implements block ciphers (AES and DES) and HASH function (SHA). Cryptoraptor [59] is a reconfigurable cryptographic processor that implements multiple symmetric cryptographic algorithms with a peak throughput of up to 128 Gbps for AES-128. In addition to implementing encryption and decryption operations, CGRA also has some resistance to physical attacks.…”

Section: Cryptographymentioning

confidence: 99%

Architecture, challenges and applications of dynamic reconfigurable computing

Liu

Zhu

et al. 2020

J. Semicond.

View full text Add to dashboard Cite

As a computing paradigm that combines temporal and spatial computations, dynamic reconfigurable computing provides superiorities of flexibility, energy efficiency and area efficiency, attracting interest from both academia and industry. However, dynamic reconfigurable computing is not yet mature because of several unsolved problems. This work introduces the concept, architecture, and compilation techniques of dynamic reconfigurable computing. It also discusses the existing major challenges and points out its potential applications.

show abstract

Section: Cryptographymentioning

confidence: 99%

Architecture, challenges and applications of dynamic reconfigurable computing

Liu

Zhu

et al. 2020

J. Semicond.

View full text Add to dashboard Cite

show abstract

“…Coarse-grained reconfigurable architectures (CGRAs), as attractive alternatives, have become more and more popular in both academic research and commercial applications in the past few years [1]- [6]. The combination of the software flexibility and high performance of hardware contributes to the better balance of CGRAs among the key metrics, such as performance, energy efficiency and chip area.…”

Section: Introductionmentioning

confidence: 99%

A Data Prefetch and Reuse Strategy for Coarse-Grained Reconfigurable Architectures

et al. 2013

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

SUMMARYThe Coarse Grained Reconfigurable Architectures (CGRAs) are proposed as new choices for enhancing the ability of parallel processing. Data transfer throughput between Reconfigurable Cell Array (RCA) and on-chip local memory is usually the main performance bottleneck of CGRAs. In order to release this stress, we propose a novel data transfer strategy that is called Heuristic Data Prefetch and Reuse (HDPR), for the first time in the case of explicit CGRAs. The HDPR strategy provides not only the flexible data access schedule but also the high data throughput needed to realize fast pipelined implementations of various loop kernels. To improve the data utilization efficiency, a dual-bank cache-like data reuse structure is proposed. Furthermore, a heuristic data prefetch is also introduced to decrease the data access latency. Experimental results demonstrate that when compared with conventional explicit data transfer strategies, our work achieves a significant speedup improvement of, on average, 1.73 times at the expense of only 5.86% increase in area.

show abstract

“…Many kinds of CGRAs have been proposed in recent years by employing context cache, whose structures can be classified into three categories including the centralized, the distributed and the hierarchical. In MorphoSys [3] and ADRES [4,5], a centralized context cache is shared by all reconfigurable resources. In sprit of the advantage of low hardware complexity for supervision, the configuration performance degrades heavily due to access conflict in the configuration cache.…”

Section: Introductionmentioning

confidence: 99%

Coarse-grained reconfigurable architecture with hierarchical context cache structure and management approach

Wang

Cao

Liu

et al. 2017

IEICE Electron. Express

View full text Add to dashboard Cite

This paper proposes a novel coarse-grained reconfigurable array (CGRA) with hierarchical context cache structure and efficient cache management approaches, including time-frequency weighted (TFW) context cache replacement strategy and context multi-casting (CMC) mechanism. By fully exploiting inherent configuration features, the configuration performance is improved by 18.2% with half context memory cost. Our CGRA was implemented under the process of TSMC 65 nm, which can work at the frequency of 200 MHz with the area of 23.2 mm 2 . Compared to the previous CGRAs, our work has the advantage of 3.8∼12× performance improvement and 2.3∼15.7× energy efficiency increase.

show abstract

Mapping an H.264/AVC decoder onto the ADRES reconfigurable architecture

Cited by 20 publications

References 5 publications

Architecture, challenges and applications of dynamic reconfigurable computing

Architecture, challenges and applications of dynamic reconfigurable computing

A Data Prefetch and Reuse Strategy for Coarse-Grained Reconfigurable Architectures

Coarse-grained reconfigurable architecture with hierarchical context cache structure and management approach

Contact Info

Product

Resources

About