Manufacturing AlGaAs/GaAs HBTs on 100 mm wafers

Huang, Rong‐Ting; Nelson, Don; Mony, S.; Tang, R.; Pierson, R.; Penney, J.; Sahai, R.

doi:10.1109/gaas.1993.394437

Cited by 5 publications

(1 citation statement)

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“…For a switching current of 2 mA, unloaded gate delays on the order of 20 ps and rise times of 30-40 ps are possible [4], [21]. The test chip was fabricated on 100-mm wafers [22]. Typical HBT base widths vary from 500 to 1000Å.…”

Section: Fabrication Process and Test Structuresmentioning

confidence: 99%

Accurate high-speed performance prediction for full differential current-mode logic: the effect of dielectric anisotropy

Garg

Coz

Greub

et al. 1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Integrated-circuit interconnect characterization is growing in importance as devices become faster and smaller. Along with this trend, interconnect geometry is becoming more complex, consisting of an increasing number of wiring levels. Accurate numerical extraction of three-dimensional (3-D) interconnect capacitance is essential for achieving design targets in the multigigahertz digital regime. Interconnectcapacitance extraction is complicated by the presence of inhomogeneous layers with differing dielectric constant. Dielectric anisotropy as well is common in many low-polymeric dielectrics used in high-performance IC's. A CAD procedure using the novel floating random-walk extractor QuickCAP is presented. Our procedure is efficient enough to extract a substantial amount of a chip's 3-D wiring. We include as well dielectric anisotropy and inhomogeneity. The procedure is not based on effective conductor geometry or on a finite-sized conductor library but rather on the entire 3-D layout, accounting for actual local variations in conductor separations and shapes. We then apply our procedure to an experimental circuit vehicle implemented in AlGaAs/GaAs heterojunction bipolar transistor current-mode logic. This vehicle is used to validate the accuracy of our CAD procedure in predicting circuit speed. Measured and predicted test-capacitor values and ring-oscillator propagation times agreed generally to within 2-4%. To verify results on a larger digital circuit, we analyzed all interconnects in an adder carry-chain oscillator using our procedure. Predicted propagation delays were generally within 3% of measurement.

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Section: Fabrication Process and Test Structuresmentioning

confidence: 99%

Accurate high-speed performance prediction for full differential current-mode logic: the effect of dielectric anisotropy

Garg

Coz

Greub

et al. 1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Compound Semiconductor Device Processing

Parsey

2013

Materials Science and Technology

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The sections in this article are Introduction Doping Processes Ion Implantation Diffusion Methods Epitaxial Methods Isolation Methods Mesa Etching Ion Implantation Isolation Sidegating and Backgating Diffusion Etching Techniques Wet Etching Dry Etching Ohmic Contacts Schottky Barriers and Gates Annealing Dielectrics and Interlayer Isolation Resistors Metallization and Liftoff Processes Metallization Liftoff Processes Backside Processing and Die Separation Backside Processing Die Separation

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